CY7C1565KV18-500BZXI
Active and preferred
RoHS Compliant

CY7C1565KV18-500BZXI

package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1565KV18-500BZXI
CY7C1565KV18-500BZXI

Product details

  • Architecture
    QDR-II+
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    QDR-II+
  • Frequency
    500 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2.5
Recommended
OPN
CY7C1565KV18-500BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1565KV18-500BZXI is a 72-Mbit (2M × 36) 1.8 V synchronous pipelined QDR II+ SRAM with separate read and write ports and a four-word burst architecture. It supports 2.5-cycle read latency and DDR transfers on K/K clocks to 500 MHz, with CQ/CQ echo clocks and a QVLD data-valid output. I/O VDDQ ranges from 1.4 V to VDD, in a 165-ball FBGA for -40°C to +85°C industrial operation.

Features

  • QDR II+ four-word burst
  • Separate read/write data ports
  • DDR I/O on read and write ports
  • 2.5-cycle read latency (DOFF=H)
  • 1-cycle read latency (DOFF=L)
  • 550 MHz maximum clock
  • Data valid 0.45 ns from clock edge
  • Echo clocks CQ/CQ for capture
  • QVLD asserts 0.5 cycle before data
  • Programmable output impedance (RQ)
  • On-chip PLL operates down to 120 MHz
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • No bus turnaround, less contention
  • DDR at 550 MHz boosts bandwidth
  • 4-word burst cuts addr bus rate
  • Selectable latency eases timing
  • 1-cycle mode reduces read delay
  • 0.45 ns valid supports tight timing
  • CQ/CQ simplifies data capture
  • QVLD eases strobe and timing align
  • RQ matching improves signal integrity
  • PLL improves data placement accuracy
  • Depth expansion without wait states
  • JTAG speeds board test and debug

Applications

Documents

Design resources

Partner solutions

Developer community