CY7C1543KV18-400BZI
Active and preferred

CY7C1543KV18-400BZI

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CY7C1543KV18-400BZI
CY7C1543KV18-400BZI

Product details

  • Density
    72 MBit
  • Family
    QDR-II+
  • Frequency
    400 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4M x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
Recommended
OPN
CY7C1543KV18-400BZI
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 136
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 136
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1543KV18-400BZI is a 72-Mbit QDR II+ synchronous pipelined SRAM (4M × 18) with separate read and write ports for concurrent transactions and no data bus turn-around. It supports 2.0-cycle read latency and DDR I/O (900 MHz data) at up to 400 MHz clock. It runs from 1.8 V VDD (1.7–1.9 V) with 1.4 V to VDD VDDQ, and is offered in a 165-ball FBGA for industrial -40 to +85°C operation.

Features

  • Separate read and write ports
  • DDR on read and write ports
  • 450 MHz clock operation
  • 900 MHz data transfer at 450 MHz
  • Four-word burst per access
  • 2-cycle read latency (DOFF HIGH)
  • 1-cycle read latency (DOFF LOW)
  • Input clocks K and K (rising edge)
  • Echo clocks CQ and CQ for capture
  • QVLD data-valid output indicator
  • ZQ programmable output impedance
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • No bus turn-around or contention
  • Maximizes bandwidth for fast links
  • Lower address rate eases PCB routing
  • Selectable latency aids timing closure
  • Echo clocks simplify data capture
  • QVLD reduces read timing uncertainty
  • Impedance match improves signal SI
  • PLL keeps data placement accurate
  • Depth expansion without added waits
  • Byte writes avoid read-modify-write
  • VDDQ 1.4 V to VDD eases interfacing
  • JTAG speeds board bring-up and test

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