CY7C1470V33-167AXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1470V33-167AXI

Data Sheet
package

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CY7C1470V33-167AXI
CY7C1470V33-167AXI
Data Sheet

Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1470V33-167AXI
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1470V33-167AXI is a 72-Mbit (2M × 36) synchronous pipelined burst SRAM with NoBL architecture, enabling zero-wait-state back-to-back read/write transfers with data each clock. It supports 167 MHz bus operation, uses 3.135 V to 3.6 V VDD with 2.5 V or 3.3 V I/O (VDDQ), and includes byte write plus IEEE 1149.1 JTAG boundary scan. The -AXI option is a 100-pin Pb-free TQFP for -40 to 85°C industrial range.

Features

  • 72-Mbit sync pipelined burst SRAM
  • NoBL logic for zero bus latency
  • 200 MHz bus ops, zero wait states
  • Fully registered inputs and outputs
  • 3.0 ns clock-to-output (tCO)
  • On-chip burst counter, 4-beat burst
  • Linear or interleaved burst order
  • Byte write via BW[x] byte selects
  • Single 3.3 V VDD supply (3.135-3.6 V)
  • 3.3 V or 2.5 V VDDQ I/O supply
  • ZZ sleep mode; 2tCYC entry/exit
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • Zero-latency boosts throughput
  • 200 MHz supports fast datapaths
  • Registered I/O eases timing closure
  • 3.0 ns tCO cuts read data latency
  • 4-beat bursts reduce addr overhead
  • Selectable burst supports controllers
  • Byte writes speed RMW operations
  • Single 3.3 V core simplifies power
  • 2.5/3.3 V I/O fits mixed-voltage
  • ZZ mode cuts standby power (120 mA)
  • 2tCYC wake-up enables fast resume
  • JTAG scan simplifies board test

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }