CY7C1470BV25-167BZXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1470BV25-167BZXI

Data Sheet
package
ea.
in stock

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CY7C1470BV25-167BZXI
CY7C1470BV25-167BZXI
ea.
Data Sheet

Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.38 V to 2.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1470BV25-167BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1470BV25-167BZXI is a 72-Mbit (2M × 36) synchronous pipelined burst SRAM with No Bus Latency (NoBL) architecture. It runs from a single 2.5 V supply with 2.5 V I/O (VDDQ), supports up to 167 MHz clock (6.0 ns cycle), and enables true back-to-back reads/writes with no wait states. Features include byte write, linear/interleaved burst up to four transfers, ZZ sleep mode, and IEEE 1149.1 JTAG in a 165-ball Pb-free FBGA (industrial range).

Features

  • 72-Mbit sync pipelined burst SRAM
  • 2.375–2.625 V core supply (VDD)
  • 2.5 V I/O supply (VDDQ)
  • 250 MHz bus ops, zero wait states
  • tCO max 3.0 ns (250 MHz)
  • Fully registered inputs and outputs
  • Unlimited back-to-back read/write
  • On-chip burst counter, up to 4
  • Linear or interleaved burst order
  • Byte Write via BWx byte selects
  • CEN suspends operation (stall)
  • ZZ sleep mode with data integrity

Benefits

  • No wait states boosts throughput
  • 250 MHz supports fast datapaths
  • Pipelined I/O eases timing closure
  • 3.0 ns tCO reduces read latency
  • Back-to-back ops maximize bus use
  • Burst up to 4 cuts addr overhead
  • Burst order adapts to host logic
  • Byte Write avoids read-modify-write
  • CEN stalling enables clock gating
  • ZZ sleep preserves data at standby
  • Tri-state control avoids contention
  • 2.5 V supplies simplify integration

Applications

Documents

Design resources

Partner solutions

Developer community

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