CY7C1061G30-10BV1XE
Active and preferred
RoHS Compliant
Lead-free

CY7C1061G30-10BV1XE

Data Sheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1061G30-10BV1XE
CY7C1061G30-10BV1XE
Data Sheet

Product details

  • Density
    16 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 125 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    1Mb x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive(E)
  • Speed
    10 ns
Recommended
OPN
CY7C1061G30-10BV1XE
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1061G30-10BV1XE is a 16-Mbit (1 M × 16) asynchronous CMOS SRAM with embedded ECC that detects and corrects single-bit read errors. It supports 10 ns access time, operates from 2.2 V to 3.6 V over -40°C to 125°C, and uses single CE with OE/WE plus BLE/BHE byte control. Automatic CE power-down standby is specified up to 50 mA (ISB2 max). It is offered in a 48-ball VFBGA (BV) package.

Features

  • 16-Mbit (1 M x 16) SRAM
  • ECC corrects 1-bit read errors
  • 10 ns address access time (tAA)
  • 10 ns read cycle time (tRC)
  • 10 ns write cycle time (tWC)
  • Byte writes via BLE/BHE
  • VCC operating: 2.2 V to 3.6 V
  • Data retention at VCC = 1.0 V
  • ICC typ 90 mA at fMAX
  • ISB2 typ 20 mA standby
  • OE to data: 5 ns (tDOE)
  • Output High-Z when deselected

Benefits

  • Higher data integrity in SRAM reads
  • Fewer soft errors to debug in field
  • Fast reads for tight timing margins
  • Predictable read throughput
  • Fast writes for real-time logging
  • Byte writes reduce bus traffic
  • Works with 2.2 V–3.6 V rails
  • Retain data during low-power sleep
  • Lower active power at high speed
  • Lower standby power when idle
  • Faster OE improves read latency
  • High-Z simplifies bus sharing

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }