CY62187EV30LL-55BAXIT
Active and preferred
RoHS Compliant

CY62187EV30LL-55BAXIT

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CY62187EV30LL-55BAXIT
CY62187EV30LL-55BAXIT

Product details

  • Density
    64 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Operating Voltage (VCCQ) max
    3.6 V
  • Organization (X x Y)
    4M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    55 ns
OPN
CY62187EV30LL-55BAXIT
Product Status active and preferred
Infineon Package
Package Name FBGA-48 (001-50044)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
Package Name FBGA-48 (001-50044)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62187EV30LL-55BAXIT is a 64-Mbit (4M × 16) CMOS asynchronous SRAM for portable memory expansion. It operates from 2.2 V to 3.6 V across -40°C to +85°C with 55 ns access speed. Typical ICC is 15 mA at 1 MHz (38 mA max) and 45 mA typical at fMax (55 mA max). It supports easy memory expansion via CE1/CE2 and byte enables BHE/BLE. Automatic chip-enable power-down reduces standby to 8 µA typical (48 µA max). Pb-free 48-ball FBGA.

Features

  • 64-Mbit (4M × 16) SRAM
  • 55 ns read/write cycle time
  • 2.2 V to 3.6 V supply
  • 15 mA typ ICC at 1 MHz
  • 8 µA typ standby (Auto PD)
  • 48 µA max standby current
  • 48 µA max data retention current
  • Data retention at VCC = 1.5 V
  • Byte write via BLE/BHE
  • High-Z outputs with OE/CE
  • ESD > 2001 V (MIL-STD-883)
  • 20 mA output sink capability

Benefits

  • 16-bit bus boosts bandwidth
  • 55 ns access supports fast CPUs
  • 2.2–3.6 V fits many rails
  • Low ICC cuts active power
  • Auto power-down saves energy
  • µA standby extends battery life
  • 1.5 V retention backs up SRAM
  • Byte write cuts write power
  • High-Z outputs ease bus sharing
  • High ESD improves robustness
  • 20 mA sink drives loads directly
  • CMOS balances speed and power

Applications

Documents

Design resources

Developer community