CY62168EV30LL-45BVXI
Active and preferred
RoHS Compliant
Lead-free

CY62168EV30LL-45BVXI

Datasheet
package
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY62168EV30LL-45BVXI
CY62168EV30LL-45BVXI
ea.
Datasheet

Product details

  • Density
    16 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    2M x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
Recommended
OPN
CY62168EV30LL-45BVXI
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY62168EV30LL-45BVXI is a 16-Mbit (2M × 8) CMOS asynchronous SRAM for portable systems. It operates from 2.2 V to 3.6 V (3.0 V typical) and provides 45 ns access. Low-power operation includes 7 mA typical ICC at 1 MHz and automatic CE power-down with 1.5 µA typical standby (12 µA max). It supports easy memory expansion using CE1/CE2 and OE and is offered in a Pb-free 48-ball VFBGA package.

Features

  • 16-Mbit SRAM, 2M × 8
  • 45 ns read/write cycle time
  • Address to data valid 45 ns
  • OE to data valid 22 ns
  • Single supply 2.2 V to 3.6 V
  • Active current 7 mA at 1 MHz typ
  • Standby 1.5 µA typ, 12 µA max
  • Data retention at VCC down to 1.5 V
  • Retention current 10 µA max
  • CE1/CE2 chip enables, OE, WE
  • Tri-state I/O on deselect or OE
  • Input/output capacitance 10 pF max

Benefits

  • Stores 2 MB for code or buffers
  • 45 ns cuts memory access latency
  • 45 ns tAA supports fast CPUs
  • 22 ns OE speeds random reads
  • 2.2–3.6 V fits common 3 V rails
  • 7 mA at 1 MHz lowers energy use
  • µA standby extends battery life
  • 1.5 V retention keeps data on droop
  • 10 µA retention eases backup power
  • CE/OE/WE simplifies bus control
  • Tri-state enables bus sharing
  • Low capacitance eases SI margins

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }