CY62147EV18LL-55BVXIT
Active and preferred
RoHS Compliant
Lead-free

CY62147EV18LL-55BVXIT

Datasheet
package

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CY62147EV18LL-55BVXIT
CY62147EV18LL-55BVXIT
Datasheet

Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.65 V to 2.25 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
Recommended
OPN
CY62147EV18LL-55BVXIT
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62147EV18LL-55BVXIT is a 4-Mbit (256 K × 16) CMOS SRAM in a Pb-free 48-ball VFBGA, specified for 55 ns access. It operates from 1.65 V to 2.25 V over -40°C to 85°C and uses CE/OE/WE plus BLE/BHE byte enables. ICC is 2.5 mA max at 1 MHz and 20 mA max at f = fmax. Automatic power-down when deselected limits standby ISB to 7 µA max; data retention is supported at VCC = 1.0 V with ICCDR 5 µA max.

Features

  • 4-Mbit SRAM organized 256K × 16
  • 55 ns read cycle time (tRC)
  • 45 ns write cycle time (tWC)
  • 1.65 V to 2.25 V single supply
  • 2 mA active current at 1 MHz typ
  • 1 µA standby current (typ)
  • Auto power-down when deselected
  • Data retention at VCC ≥ 1.0 V
  • 0.5 µA data retention current typ
  • High-Z outputs when deselected
  • Byte enables: BLE and BHE
  • ±1 µA input/output leakage max

Benefits

  • Fits 16-bit buses in SRAM
  • 55 ns supports fast CPU access
  • 45 ns writes reduce wait states
  • Runs direct from 1.8 V rails
  • Low active power for portable use
  • µA standby extends battery life
  • Idle bus cuts power automatically
  • Keeps data with backup supply
  • µA retention enables coin cells
  • High-Z avoids bus contention
  • Byte write lowers write bandwidth
  • Low leakage improves power budget

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Documents

Design resources

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Developer community

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