Please note that this is an end of life product. See newer alternative product version Please note that this is an end of life product. See newer alternative product version
CY2309ZXC-1HT
END OF LIFE
discontinued
RoHS Compliant

CY2309ZXC-1HT

END OF LIFE
package

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CY2309ZXC-1HT
CY2309ZXC-1HT

Product details

  • Category
    Zero Delay Buffers
  • Core/IO Operating Voltages ((V))
    3.3
  • Features
    3.3V Zero Delay Buffer
  • Function
    See datasheet
  • I/O Voltage ((V))
    3.3
  • Input Frequency range
    10 MHz to 133 MHz
  • Input Type
    LVCMOS/LVTTL
  • Lead Ball Finish
    Ni/Pd/Au
  • On-chip Clock Generation (PLL)
    1
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3 V to 3.6 V
  • Output Frequency range
    10 MHz to 133 MHz
  • Output Signal Type
    LVCMOS
  • Outputs
    9
  • Peak Reflow Temp
    260 °C
  • Publish in NPSG
    N
  • Publish in PSG
    Y
  • Qualification
    Commercial
  • Spread Spectrum
    N
OPN
CY2309ZXC-1HT
Product Status discontinued
Infineon Package
PG-TSSOP-16
Package Name TSSOP-16 (51-85091)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status discontinued
Infineon Package
PG-TSSOP-16
Package Name TSSOP-16 (51-85091)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY2309ZXC-1HT is a 3.3 V zero delay buffer with nine LVCMOS outputs and an on-chip PLL for clock distribution. It supports 10.0 to 133.0 MHz input and output frequencies, operates from 3.0 to 3.6 V supply, and covers a 0 to 70°C commercial temperature range. Input type is LVCMOS/LVTTL, output is LVCMOS, and the device is RoHS compliant with Ni/Pd/Au lead finish.

Features

  • Zero input-output propagation delay
  • 60-ps typical cycle-to-cycle jitter
  • Multiple low skew outputs
  • On-chip PLL for input clock locking
  • Test mode bypasses PLL (CY2309)
  • Power-down mode with <25 μA current
  • Device-to-device skew <700 ps
  • Output-to-output skew 85 ps typical
  • One input drives multiple outputs
  • Adjustable input-output delay via
  • Wide load capacitance support
  • Duty cycle 40-60% at 66.67 MHz

Benefits

  • Zero delay ensures precise clock timing
  • Low jitter improves signal integrity
  • Low skew enables synchronous systems
  • PLL locks input for stable outputs
  • Test mode simplifies system validation
  • Power-down saves energy in idle state
  • Low device skew supports clock
  • Tight output skew improves timing margin
  • One input simplifies clock routing
  • Adjustable delay enables system tuning
  • Supports diverse system loads
  • Stable duty cycle aids timing accuracy

Applications

Documents

Design resources

Partner solutions

Developer community

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