EZ-PD™ PAG2P Primary Side Controller
Primary HV start-up controller
EZ-PD™ PAG2P is a primary start-up controller and is designed to receive PWM signals from EZ-PD™ PAG2S, which performs the PWM regulation. It provides HV start-up, PET receiver via CYPET121, boosts VCC, low-side NFET gate driver, and high-side logical driver. EZ-PD™ PAG2P supports both X-cap discharge and non-X-cap discharge mode. It pairs with EZ-PD™ PAG2S-AC to support ACF converters and EZ-PD™ PAG2S-QZ to support QR-ZVS flyback converters.
- Integrated high-voltage start-up
- Integrated low-side gate driver
- Integrated high-side driver
- Integrated VCC boost switch
- Programmable soft-start
- Support x-cap discharge mode
- Brown-in/out and line OVP/UVP
- Support OCP and SCP
- Startup secondary VBUS OVP
- Pairs with CYPET121 PET
- Integrated PET receiver
- USB-C adapter and charger
- USB-C wall outlet
- USB-C travel adapter
Once the line voltage is within normal operating range, the gate driver starts switching. An internal high-voltage JFET takes current from the HV pin to charge up the VCC capacitor during the start-up phase. An auxiliary winding from the flyback transformer will be used to supply EZ-PD™ PAG2P after the start-up phase and no current will be sourced from the HV pin after the start-up phase. The soft-start feature allows EZ-PD™ PAG2P to gradually increase the output voltage of the flyback converter till the secondary side takes control of the regulation. Soft-start is used during the initial start-up sequence and fault conditions. The duration of the soft-start is controlled by an external capacitor connected to the SS pin and the frequency of the soft-start is determined by an external resistor connected to the RT pin.
For the X-cap discharge mode, the HV pin of EZ-PD™ PAG2P is connected to the AC mains through diodes. A UVLO is included to prevent false startup when the line voltage is low and keeps the primary FET off. An OVP is implemented to shut the primary FET off when line voltage exceeds V_HV_OVRISE. EZ-PD™ PAG2P discharges the X-capacitor via the HV pin when the X-cap mode is enabled. For the non-X-cap discharge mode, the HV pin is connected to the DC rectified voltage. The pin powers EZ-PD™ PAG2P during startup. Additionally, it provides undervoltage and overvoltage protection via the HV pin. As long as the fault is present, protection is enabled.
During the close loop control phase, EZ-PD™ PAG2P performs synchronization with the secondary-side pulses from the PULSEIN pin when the secondary side is active. The PWM signals from EZ-PD™ PAG2S are coupled to the primary side using a pulse edge transformer (PET). CYPET121 is a PET that provides 3k VAC hipot-isolation and 8 mm creepage distance. CYPET121 could also be manufactured by third-party manufacturers following CYPET121 specifications.
The BSW pin of EZ-PD™ PAG2P is connected to an external inductor where the other terminal is connected to an auxiliary winding from the flyback transformer through a diode. The BSW pin is also connected to the VCC pin through an external diode to form a boost regulator topology together with the inductor. Once EZ-PD™ PAG2S controls the primary side gate driver, the boost converter will take over from the high-voltage start-up circuit to supply VCC during the closed loop. A current coming from HV pin charges the VCC capacitor during the start-up phase. Once VCC is increased up to 7.5 V, the internal LDO is ready. Then, EZ-PD™ PAG2P spends some time on initialization. After finishing initialization, the free-running oscillator comes in and V_AUXIN is built up gradually. VCC boost converter is enabled and VCC is regulated to V_VCCREG unless V_AUXIN is higher than V_VINOV. The auxillary winding (V_AUXIN) takes over supplying VCC when V_AUXIN is higher than V_VINOV. The boost converter resumes switching when V_AUXIN is below V_VINOV.
