Active and preferred
RoHS Compliant
Lead-free

S25FS512SDSMFV010

Data Sheet
package
software

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S25FS512SDSMFV010
S25FS512SDSMFV010
Data Sheet

Product details

  • Density
    512 MBit
  • Family
    FS-S
  • Interface Bandwidth
    80 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / 80
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Matte Tin Plating
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
Recommended
OPN
S25FS512SDSMFV010
Product Status active and preferred
Infineon Package
PG-DSO-16
Package Name SOIC-16 (002-15547)
Packing Size 2400
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-DSO-16
Package Name SOIC-16 (002-15547)
Packing Size 2400
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S25FS512SDSMFV010 is a 512 Mb SPI Multi-I/O NOR flash memory using 65-nm MIRRORBIT™ technology and Eclipse architecture. It delivers up to 80 MB/s read rates (DDR Quad I/O) and supports 512-byte page programming. Operating from 1.7 V to 2.0 V, it covers industrial and automotive temperature ranges from -40°C to +125°C (AEC-Q100 Grade 1). Features include hybrid and uniform sector erase, internal ECC, block protection, and 20-year data retention.

Features

  • SPI with multi-I/O support
  • DDR and SDR clocking options
  • 24- or 32-bit addressing
  • Compatible with S25FL SPI families
  • Multiple read modes: Normal, Fast, Dual
  • Burst wrap and XIP support
  • 256/512-byte page programming buffer
  • Program and erase suspend/resume
  • Internal ECC with single bit correction
  • Hybrid and uniform sector erase options
  • 100,000 program-erase cycles min
  • 20 year data retention min

Benefits

  • Flexible interface for diverse host
  • High-speed data transfer and boot performance
  • Supports large address spaces for modern
  • Easy migration from legacy SPI designs
  • Optimized for fast and efficient data access
  • Enables execute-in-place (XIP) applications
  • Efficient programming for fast updates
  • Minimized downtime during program/erase
  • Enhanced data reliability and integrity
  • Flexible memory management for varied needs
  • Long device lifetime for demanding use
  • Reliable data storage for mission-critical

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }