CY7C4141KV13-667FCXC
Active and preferred
RoHS Compliant
Lead-free

CY7C4141KV13-667FCXC

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CY7C4141KV13-667FCXC
CY7C4141KV13-667FCXC

Product details

  • Architecture
    QDR-IV
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    Y
  • Family
    QDR-IV
  • Frequency
    667 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.26 V to 1.34 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    5
Recommended
OPN
CY7C4141KV13-667FCXC
Product Status active and preferred
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 300
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 300
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C4141KV13-667FCXC is a 144-Mbit QDR-IV HP SRAM in a 4M × 36 organization, optimized for random transactions with dual independent bidirectional DDR data ports. It supports up to 667 MHz clock (1334 MT/s RTR) with two-word burst, SDR control and DDR address signaling. On-die termination, bus inversion, address parity, and JTAG 1149.1 test access are included. On-chip ECC corrects single-bit errors.

Features

  • 144-Mbit QDR-IV HP SRAM
  • Total rate 1334 MT/s
  • Max operating freq 667 MHz
  • Read latency 5 clock cycles
  • Write latency 3 clock cycles
  • Two-word burst on all accesses
  • Dual bidirectional DDR data ports
  • Concurrent read/write on both ports
  • DDR address, SDR control signaling
  • POD, HSTL, SSTL I/O (JESD)
  • On-die termination, programmable
  • ECC, bus inversion, address parity

Benefits

  • 144 Mbit reduces external memory
  • 1334 MT/s boosts throughput
  • 667 MHz supports fast clocks
  • 5-cycle reads cut wait states
  • 3-cycle writes reduce latency
  • Two-word burst improves efficiency
  • Dual ports increase concurrency
  • Full-duplex access reduces stalls
  • DDR address enables high RTR
  • JESD I/O eases board interfacing
  • ODT simplifies signal integrity
  • ECC/parity reduces data corruption

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