CY7C25652KV18-400BZXI
Active and preferred
RoHS Compliant

CY7C25652KV18-400BZXI

Data Sheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C25652KV18-400BZXI
CY7C25652KV18-400BZXI
Data Sheet

Product details

  • Density
    72 MBit
  • Family
    QDR-II+, ODT
  • Frequency
    400 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
Recommended
OPN
CY7C25652KV18-400BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 136
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 136
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C25652KV18-400BZXI is a 72-Mbit QDR II+ synchronous pipelined SRAM in a 2M × 36 organization with separate read and write ports for concurrent transactions. It supports a four-word burst, 2.5-cycle read latency, and DDR interfaces on both ports (data transfer on every clock edge). It runs from 1.7–1.9 V VDD with 1.4 V to VDD VDDQ, in a 165-ball FBGA, industrial -40 to +85°C range.

Features

  • 550 MHz clock (1100 MHz DDR data)
  • Separate read and write data ports
  • Concurrent read/write transactions
  • Four-word burst architecture
  • 2.5-cycle read latency (DOFF HIGH)
  • 1-cycle read latency mode (DOFF LOW)
  • Two input clocks (K and K)
  • Echo clocks CQ/CQ for data capture
  • QVLD pin indicates valid read data
  • On-die termination for D/BWS/K
  • PLL runs down to 120 MHz
  • Core VDD 1.7 V to 1.9 V

Benefits

  • High bandwidth for fast DSP/ASIC
  • No bus turn-around delays
  • Read and write run in parallel
  • Lower address bus frequency
  • Deterministic 2.5-cycle reads
  • 1-cycle reads for low latency
  • Simpler DDR timing with K/K
  • Easier high-speed data capture
  • QVLD reduces timing margin effort
  • ODT cuts external termination BOM
  • PLL improves data placement margin
  • 1.8 V core reduces power vs 2.5 V

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }