CY7C1460KV33-167AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1460KV33-167AXC

Data Sheet
package

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CY7C1460KV33-167AXC
CY7C1460KV33-167AXC
Data Sheet

Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    36 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    1Mb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1460KV33-167AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1460KV33-167AXC is a 3.3 V, 36-Mbit (1M × 36) synchronous pipelined burst SRAM with No Bus Latency (NoBL) for back-to-back read/write transfers every clock. It supports 167 MHz operation with 3.4 ns max access time, fully registered inputs/outputs, byte writes, and linear or interleaved bursts. VDDQ supports 3.3 V or 2.5 V I/O. It is offered in 100-pin TQFP, commercial 0°C to +70°C.

Features

  • 36-Mbit sync pipelined SRAM
  • NoBL logic, zero wait-state bursts
  • Supports 250-MHz bus operation
  • Clock-to-output tCO max 2.5 ns
  • Fully registered I/O on rising clock
  • On-chip burst counter, up to 4 beats
  • Linear or interleaved burst sequence
  • Byte write with BW[x] byte selects
  • Self-timed synchronous write
  • CEN clock enable suspends operation
  • ZZ sleep mode with data retention
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • Zero wait states boost throughput
  • 250 MHz supports fast datapaths
  • 2.5 ns tCO reduces read latency
  • Registered I/O eases timing closure
  • 4-beat bursts cut address toggling
  • Burst mode fits cacheline transfers
  • Byte writes simplify RMW updates
  • Self-timed writes simplify control
  • CEN enables quick pause/resume
  • ZZ sleep lowers standby power
  • Data retained in sleep protects data
  • JTAG scan speeds board test

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }