CY7C1371KV33-133AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1371KV33-133AXC

package
ea.
in stock

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CY7C1371KV33-133AXC
CY7C1371KV33-133AXC
ea.

Product details

  • Architecture
    NoBL, Flow-through
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    18 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    133 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.135 V to 3.6 V
  • Organization (X x Y)
    512Kb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1371KV33-133AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The CY7C1371KV33-133AXC is an 18-Mbit synchronous flow-through burst SRAM (512K × 36) with NoBL architecture for true back-to-back read/write transfers with no wait states. It supports bus operation up to 133 MHz with 6.5 ns clock-to-data valid, linear or interleaved 4-beat bursts, byte write control, and on-chip ECC. Commercial grade, 3.3 V core with 2.5 V/3.3 V VDDQ I/O, in 100-pin TQFP.

Features

  • NoBL architecture, no dead cycles
  • Up to 133 MHz, zero wait states
  • 6.5 ns clock-to-output (133 MHz)
  • Data on every clock cycle
  • Burst: linear or interleaved
  • Byte write via BWx + WE
  • Registered synchronous inputs
  • Self-timed synchronous writes
  • Asynchronous OE output control
  • 3 chip enables (CE1/CE2/CE3)
  • Sleep mode via ZZ; 2tCYC entry/exit
  • On-chip ECC lowers soft errors

Benefits

  • Seamless read/write switching
  • High throughput at 133 MHz bus
  • Faster access for tight timing
  • Predictable per-cycle transfers
  • Efficient burst data streaming
  • Update bytes without full writes
  • Simplifies synchronous timing
  • Reliable writes at high speed
  • Easy bus tri-state control
  • Simple bank selection/expansion
  • Cut standby power in sleep
  • Better data integrity in radiation

Applications

Documents

Design resources

Partner solutions

Developer community

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