CY7C10612G30-10ZSXIT
Active and preferred
RoHS Compliant
Lead-free

CY7C10612G30-10ZSXIT

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CY7C10612G30-10ZSXIT
CY7C10612G30-10ZSXIT

Product details

  • Density
    16 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns
OPN
CY7C10612G30-10ZSXIT
Product Status active and preferred
Infineon Package
Package Name TSOP-II-54 (51-85160)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
Package Name TSOP-II-54 (51-85160)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C10612G30-10ZSXIT is a 16-Mbit (1M × 16) asynchronous CMOS SRAM with embedded ECC for single-bit error correction. It runs from 3.3 V ± 0.3 V over -40 to 85°C, with 10 ns maximum access time. Operating current is 110 mA max at 100 MHz, and CE automatic power-down supports CMOS standby up to 30 mA. It provides 16-bit I/O with byte enables in a 54-pin TSOP II tape-and-reel package.

Features

  • 16-Mbit SRAM, 1M x 16 array
  • 10 ns address access time (tAA)
  • 10 ns read cycle time (tRC)
  • Embedded ECC with 1-bit correction
  • ERR output flags ECC event (GE)
  • Byte write enable (BLE/BHE)
  • OE/CE-controlled 3-state outputs
  • 3.3 V ±0.3 V single-supply VCC
  • TTL-compatible input/output levels
  • 1.0 V data retention mode
  • ICC 90 mA typ at 100 MHz
  • TA -40°C to +85°C operating

Benefits

  • 10 ns reads reduce memory latency
  • 16-bit bus increases throughput
  • ECC improves data integrity
  • ERR pin supports fault monitoring
  • Byte writes cut write bandwidth
  • 3-state outputs enable bus sharing
  • 3.3 V rail simplifies power design
  • TTL I/O eases logic interfacing
  • Retention preserves data at low V
  • 90 mA typ helps limit power draw
  • Power-down standby saves energy
  • -40°C to +85°C boosts reliability

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