CY7C1011G30-12ZSXET
Active and preferred
RoHS Compliant
Lead-free

CY7C1011G30-12ZSXET

Data Sheet
package

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CY7C1011G30-12ZSXET
CY7C1011G30-12ZSXET
Data Sheet

Product details

  • Density
    2 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 125 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    128Kb x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive(E)
  • Speed
    12 ns
Recommended
OPN
CY7C1011G30-12ZSXET
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1011G30-12ZSXET is a 2-Mbit (128K × 16) asynchronous CMOS SRAM with embedded ECC for single-bit error correction. It operates from 2.2 V to 3.6 V across -40°C to 125°C (Automotive-E) and is AEC-Q100 qualified. The 12 ns speed grade uses CE/OE/WE control with BLE/BHE byte writes and offers ICC 40 mA typ, ISB2 6 mA typ. It is supplied in a 44-pin TSOP II tape-and-reel package for automotive ECUs.

Features

  • 2-Mbit SRAM, 128K × 16-bit
  • Embedded ECC, single-bit correct
  • Read cycle time tRC 10 ns
  • OE LOW to data tDOE 4.5 ns
  • Byte write via BHE/BLE pins
  • 2.2 V to 3.6 V supply (VCC)
  • 1.0-V data retention mode
  • Auto CE power-down (ISB1/ISB2)
  • Standby current ISB2 6 mA typ
  • High-Z outputs when deselected
  • TTL-compatible inputs and outputs
  • SER rate < 0.1 FIT/Mb

Benefits

  • 2-Mbit fits code/data buffers
  • ECC helps protect against bit flips
  • 10 ns cycles enable fast SRAM reads
  • 4.5 ns OE cuts read access latency
  • Byte writes reduce bus traffic
  • 2.2–3.6 V works with 3.3 V rails
  • Retention keeps data at low VCC
  • Auto power-down cuts idle power
  • 6 mA standby eases power budgets
  • High-Z enables easy bus sharing
  • TTL I/O simplifies logic interface
  • Low SER improves data integrity

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Documents

Design resources

Partner solutions

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{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }