CY62146ELL-45ZSXIT
Active and preferred
RoHS Compliant

CY62146ELL-45ZSXIT

Datasheet
package
ea.
in stock

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CY62146ELL-45ZSXIT
CY62146ELL-45ZSXIT
ea.
Datasheet

Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    5.5 V
  • Operating Voltage range
    4.5 V to 5.5 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns
Recommended
OPN
CY62146ELL-45ZSXIT
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY62146ELL-45ZSXIT is a 4-Mbit (256K × 16) CMOS static RAM for 5 V systems, specified for 45 ns access. It operates from 4.5 V to 5.5 V and supports byte writes via BHE/BLE with CE/OE/WE control and high-Z outputs when deselected. Ultra-low power includes 2.5 µA typ (7 µA max) standby with automatic CE power-down and 3.5 mA typ active current at 1 MHz, in a Pb-free 44-pin TSOP II.

Features

  • 256K × 16 CMOS static RAM
  • 45 ns read/write cycle time
  • 4.5 V to 5.5 V VCC operation
  • 3.5 mA typ ICC at 1 MHz
  • 2.5 µA typ standby (CE HIGH)
  • 7 µA max standby current
  • Automatic CE power-down (ISB2)
  • Data retention at VCC = 2 V
  • ICCDR max 8.8 µA at 2 V
  • Byte write via BHE/BLE
  • TTL-compatible input levels
  • Tri-state outputs via OE/CE

Benefits

  • Fast 45 ns boosts CPU access
  • 5 V rail fits legacy designs
  • Low 3.5 mA cuts active power
  • 2.5 µA standby extends battery
  • Auto power-down saves energy
  • 2 V retention preserves data
  • 8.8 µA max lowers backup drain
  • Byte enables reduce write power
  • OE/CE tri-state eases bus sharing
  • TTL inputs simplify interfacing
  • High-Z prevents bus contention
  • SRAM avoids refresh complexity

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