Please note that this is an end of life product. See newer alternative product version Please note that this is an end of life product. See newer alternative product version
CY23EP09SXI-1H
END OF LIFE
discontinued
RoHS Compliant

CY23EP09SXI-1H

END OF LIFE
package

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CY23EP09SXI-1H
CY23EP09SXI-1H

Product details

  • Category
    Zero Delay Buffers
  • Core/IO Operating Voltages ((V))
    2.5/3.3
  • Features
    2.5V or 3.3V,10- 220 MHz, Low Jitter, 9 Output Zero Delay Buffer
  • Function
    See datasheet
  • I/O Voltage ((V))
    2.5/3.3
  • Input Frequency range
    10 MHz to 220 MHz
  • Input Type
    LVCMOS/LVTTL
  • Lead Ball Finish
    Pure Sn
  • On-chip Clock Generation (PLL)
    1
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.3 V to 3.6 V
  • Output Frequency range
    10 MHz to 220 MHz
  • Output Signal Type
    LVCMOS
  • Outputs
    9
  • Peak Reflow Temp
    260 °C
  • Publish in NPSG
    N
  • Publish in PSG
    Y
  • Qualification
    Industrial
  • Spread Spectrum
    N
OPN
CY23EP09SXI-1H
Product Status discontinued
Infineon Package
PG-DSO-16
Package Name SOIC-16 (51-85068)
Packing Size 480
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status discontinued
Infineon Package
PG-DSO-16
Package Name SOIC-16 (51-85068)
Packing Size 480
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY23EP09SXI-1 H is a high-drive, nine-output zero delay buffer designed for industrial applications, supporting 2.5 V or 3.3 V operation and input/output frequencies from 10 MHz to 220 MHz. It features LVCMOS/LVTTL input, LVCMOS output, on-chip PLL for clock generation, and low jitter performance. The device operates from 2.3 V to 3.6 V across a -40°C to 85°C temperature range, is RoHS compliant, and is available in a 16-pin SOIC package.

Features

  • Zero input-output propagation delay
  • 45 ps typical output-output skew
  • 25 ps typical cycle-to-cycle jitter
  • 15 ps typical period jitter
  • On-chip PLL with internal feedback
  • One input drives nine outputs (4+4+1)
  • Selectable output banks, three-state
  • Standard and high drive strength options
  • Power-down mode with <25 uA current
  • Closed-loop bandwidth up to 1.5 MHz
  • Output impedance: 29-41 Ohm (typical)
  • Input capacitance: 5 pF (typical)

Benefits

  • Zero delay ensures precise clock
  • 45 ps skew enables tight timing margins
  • 25 ps jitter supports signal integrity
  • 15 ps period jitter improves clock
  • PLL feedback maintains output stability
  • Nine outputs simplify clock distribution
  • Selectable banks offer design
  • High drive supports demanding loads
  • Power-down saves energy in idle mode
  • Wide bandwidth supports fast signals
  • Low output impedance reduces signal loss
  • Low input capacitance eases integration

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