CY7C1380KV33-167AXIT
Active and preferred
RoHS Compliant
Lead-free

CY7C1380KV33-167AXIT

Data Sheet
package

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CY7C1380KV33-167AXIT
CY7C1380KV33-167AXIT
Data Sheet

Product details

  • Architecture
    Standard Sync, Pipeline SCD
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    18 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.135 V to 3.6 V
  • Organization (X x Y)
    512Kb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2
Recommended
OPN
CY7C1380KV33-167AXIT
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 750
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 750
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1380KV33-167AXIT is an 18-Mbit pipelined SRAM organized as 512K × 36 with registered inputs/outputs and an internal 2-bit burst counter. It uses a 3.3 V core supply and 2.5 V or 3.3 V I/O, and supports synchronous self-timed writes, byte writes, and 3-1-1-1 burst accesses controlled by ADSP/ADSC and ADV. The 167 MHz industrial grade is in a 100-pin Pb-free TQFP for -40°C to +85°C operation.

Features

  • Bus operation up to 250 MHz
  • 2.5 ns clock-to-output (tCO)
  • Registered I/O for pipelining
  • 3-1-1-1 burst access
  • Linear or interleaved burst order
  • 2-bit on-chip burst counter
  • Byte write via BWE and BWX
  • Global write (GW) all bytes
  • Common I/O; async OE tri-state
  • ZZ sleep mode with data retention
  • Core VDD 3.135 V to 3.6 V
  • I/O VDDQ 2.375–2.625 V or 3.3 V

Benefits

  • 250 MHz supports fast SRAM buses
  • 2.5 ns tCO cuts read latency
  • Pipelining improves throughput
  • 3-1-1-1 boosts burst bandwidth
  • Burst modes fit more processors
  • Auto increment reduces glue logic
  • Byte writes reduce write traffic
  • GW simplifies full-word updates
  • Tri-state OE enables bus sharing
  • ZZ mode lowers standby power
  • 3.135–3.6 V eases power design
  • 2.5/3.3 V I/O eases interfacing

Applications

Documents

Design resources

Partner solutions

Developer community

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