CY62157G30-45BVXAT
Active and preferred
RoHS Compliant
Lead-free

CY62157G30-45BVXAT

Data Sheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY62157G30-45BVXAT
CY62157G30-45BVXAT
Data Sheet

Product details

  • Alarms
    N
  • Density
    8 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512Kb x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive(A)
  • Real Time Clock
    N
  • Speed
    45 ns
  • Watchdog Timer
    N
Recommended
OPN
CY62157G30-45BVXAT
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62157G30-45BVXAT is an AEC-Q100 qualified 8-Mbit (512K × 16) asynchronous SRAM with embedded ECC for single-bit error correction. It operates from 2.2 V to 3.6 V over –40°C to +85°C and supports 45 ns access. Typical standby current is 5 µA (35 µA max), with automatic power-down at 1.4 µA typ (6.5 µA max). Dual chip-enable and BHE/BLE byte enables support 8-/16-bit access in automotive ECUs.

Features

  • 8-Mbit SRAM (512K x 16)
  • ECC corrects single-bit errors
  • 45 ns/55 ns read/write cycles
  • VCC 1.65-2.2 V or 2.2-3.6 V
  • 5 µA typical standby current
  • 35 µA max standby current
  • 16-bit I/O bus (I/O0 to I/O15)
  • Byte write with BHE/BLE enables
  • Dual chip-enable inputs CE1/CE2
  • I/O Hi-Z on deselect or OE high
  • Input/output leakage ±1 µA
  • 1.5-V data retention support

Benefits

  • ECC helps prevent data corruption
  • 45 ns enables fast CPU reads
  • Two VCC ranges ease rail reuse
  • 5 µA standby extends battery life
  • 35 µA max simplifies power budget
  • 16-bit bus increases data bandwidth
  • Byte writes reduce bus transactions
  • Dual CE supports easy bus sharing
  • Hi-Z outputs avoid bus contention
  • ±1 µA leakage lowers static loss
  • Data retention keeps state at 1.5 V
  • Standard OE/WE controls simplify HW
Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }