TRAVEO™ II decoder

TRAVEO™ II documentation

Documentation	Family		Level of security
Datasheet	CYT2B7	CYT2B7 Datasheet 32-bit Arm® Cortex®-M4F Microcontroller Traveo™ II Family	Public
	CYT4BF	CYT4BF Datasheet 32-bit Arm® Cortex®-M7 Microcontroller Traveo™ II Family	Public
	CYT2B9	CYT2B9 Datasheet 32-bit Arm® Cortex®-M4F Microcontroller Traveo™ II Family	Public
	CYT3BB/4BB	CYT3BB/4BB Datasheet 32-bit Arm® Cortex®-M7 Microcontroller Traveo™ II Family	Public
	CYT2BL	CYT2BL Datasheet 32-bit Arm® Cortex®-M7 Microcontroller Traveo™ II Family	Confidential NDA needed
	CYT2B6	CYT2B6 Datasheet 32-bit Arm® Cortex®-M7 Microcontroller Traveo™ II Family	Confidential NDA needed

TRAVEO™ T2G Product Overview

Documentation	Family		Level of security
Product Overview	CYT2B6/2B7/2B9/2BL	Traveo™ II CYT2B6/2B7/2B9/2BL Series Microcontrollers for Automotive Body Control Product Overview	Public
Product Overview	CYT4BB/4BF	Traveo™ II CYT4BB/4BF Series Microcontrollers for Automotive Body Control Product Overview	Public

TRAVEO™ T2G Technical Reference Manuals

Documentation	Family		Level of security
Technical Reference Manual (TRM)	TVII-B-H-4M	Traveo_II_TVII_B_H_4M Technical Reference Manual	Public
	TVII-B-E-4M	Traveo_II_TVII_B_H_4M Technical Reference Manual	Confidential NDA needed
	TVII-B-E-1M	Traveo_II_TVII_B_E_1M Technical Reference Manual	Public
		Traveo II Automotive Body Controller Entry Family Architecture	Public
		Traveo II Automotive Body Controller High Family Architecture Technical Reference Manual	Public
	TVII-B-E-2M	Traveo II- TVII_B_E_2M Technical Reference Manual	Public
	TVII-B-H-8M	Traveo_II_TVII_B_H_8M Technical Reference Manual	Public

TRAVEO™ T2G Customer Training Workshops

Documentation	Document Title	Level of security
Trainings	Traveo™ II I/O System	Public
	Traveo™ II Boot	Public
	Traveo™ II Ethernet Mac	Public
	Traveo™ II Sample Driver Library	Public
	Traveo™ II Body High and Cluster 2D SRAM Interface	Public
	Traveo™ II Nonvolatile Memory Programming	Public
	Traveo™ II Timer/Counter/Pulse-Width Modulator (TCPWM)	Public
	Traveo™ II Chip Operational Modes	Public
	Traveo™ II Device Security	Public
	Traveo™ II Body Entry SRAM Interface	Public
	Traveo™ II Program and Debug Interface	Public
	Traveo™ II SAR ADC	Public
	Traveo™ II Audio Digital Analog Converter	Public
	Traveo™ II Sound Generator	Public
	Traveo™ II Mixer	Public
	Traveo™ II Pulse Width Modulation (PWM) Interface	Public
	Traveo™ II Time Division Multiplexed (TDM)/Inter-IC sound (I2S) Interface	Public
	Traveo™ II Graphics Subsystem	Public
	Traveo™ II Clock Extension Peripheral Interface (CXPI)	Public
	Traveo™ II FlexRay	Public
	Traveo™ II Serial Memory Interface (SMIF)	Public
	Traveo™ II Audio Subsystem	Public
	Traveo™ II SDHC Host Controller	Public
	Traveo™ II Trigger Multiplexer	Public
	Traveo™ II Event Generator	Public
	Traveo™ II Local Interconnect Network (LIN)	Public
	Traveo™ II Serial Communication Block (SCB)	Public
	Traveo™ II CAN FD Controller	Public
	Traveo™ II Real-Time Clock	Public
	Traveo™ II Watchdog Timer	Public
	Traveo™ II Reset System	Public
	Traveo™ II Body High and Cluster 2D Clock System	Public
	Traveo™ II Body Entry Clock System	Public
	Traveo™ II Device Power Modes	Public
	Traveo™ II Automotive Cluster 2D Power Supply and Monitoring	Public
	Traveo™ II Body Controller High Power Supply and Monitoring	Public
	Traveo™ II Power Supply and Monitoring	Public
	Traveo™ II Fault Subsystem	Public
	Traveo™ II Interrupts	Public
	Traveo™ II Flash	Public
	Traveo™ II Automotive Body Controller Entry/High and Cluster 2D Family Overview	Public
	Traveo™ II Direct Memory Access (DMA)	Public
	Traveo™ II Protection Units	Public
	Traveo™ II Inter-Processor Communication (IPC)	Public
	Traveo™ II Body High and Cluster 2D CPU Subsystem (CPUSS)	Public
	Traveo™ II Body Entry CPU Subsystem (CPUSS)	Public

TRAVEO™ T2G Programming Specs

Documentation	Family	Level of Security
Programming Specifications	Traveo^TM II MCU Programming Specifications	Confidential NDA needed

TRAVEO™ T2G Errata sheets

Documentation	Family		Level of security
Errata Sheets	CYT2B6	CYT2B6_D_errata_rev1.0	Confidential NDA needed
	CYT2B7	CYT2B7_D_errata_rev1.3	Confidential NDA needed
	CYT2B9	CYT2B9_C_errata_rev1.4	Confidential NDA needed
	CYT2BL	CYT2BL_A_errata_rev1.1	Confidential NDA needed
	CYT2BB_4BB	CYT3BB_4BB_B_errata_rev1.3	Confidential NDA needed
	CYT4BF	CYT4BF_D_errata_rev1.3	Confidential NDA needed

TRAVEO™ T2G Simulation Tools

Documentation	Family		Level of security
IBIS	CYT3_4BB (TVII-B-H-4M)	Traveo II CYT4BB IBIS	Public
	CYT2B7 (TVII-B-E-1M)	Traveo II CYT2B7 IBIS	Public
	CYT2B9 (TVII-B-E-2M)	Traveo II CYT2B9 IBIS	Public
	CYT4BF (TVII-B-H-8M)	Traveo II CYT4BF IBIS	Public

TRAVEO™ T2G Test Board

Documentation	Family	Document Title	Level of security
User Guide	CYTVII-B-H-4M-272-CPU	Traveo™ CYTVII-B-H-4M-272-CPU	Public
	CYTVII-B-H-8M-320	Traveo™ CYTVII-B-H-8M-320	Public
	CYTVII-B-E-1M-SK	Traveo™ II CYTVII-B-E-1M-SK	Public
	CYTVII-B-H-8M-176-CPU	Traveo™ II CYTVII-B-H-8M-176-CPU	Public
Quick Start Guide	CYTVII-B-E-BB	Traveo™ CYTVII-B-E-BB	Public
	CYTVII-B-E-176-SO	Traveo™ II CPU BOARD CYTVII-B-E-176-SO	Public
	CYTVII-B-E-1M-176-CPU	Traveo™ II CPU BOARD CYTVII-B-E-1M-176-CPU	Public
	CYTVII-B-E-2M-176-CPU	Traveo™ II CPU BOARD CYTVII-B-E-2M-176-CPU	Public
	CYTVII-B-H-8M-320-BGA CPU	Traveo™ II CPU BOARD CYTVII-B-H-8M-320-BGA CPU	Public
	CYTVII-B-E-100-SO	Traveo™ II CYTVII-B-E-100-SO	Public

TRAVEO™ T2G Software

Documentation		Level of security
SampleDriver Library (SDL)	Traveo™ II Sample driver Library 7.1.0	Public
	Traveo™ II TVII Sample Driver Library 7.1.0 SW Utilities	Public
	Traveo™ II sample driver library code example	Public
	Traveo™ II Sample Driver Library Release Note	Public
	Traveo™ II SDL known Issue	Public
	Traveo II- TVII_B_E_2M Technical Reference Manual	Public
	Traveo_II_TVII_B_H_8M Technical Reference Manual	Public

TRAVEO™ T2G Flash programmer

Documentation		Level of security
Release Note	Flash Utility Release Notes	Public
Zip_file	Auto Flash Utility	Public

TRAVEO™ T2G Application Notes

AN220242 - Flash Accessing Procedure for Traveo II Family

AN220190 - HOW TO USE RTC IN TRAVEO II FAMILY

AN225401 - HOW TO USE SERIAL COMMUNICATIONS BLOCK (SCB) IN TRAVEO II FAMILY

AN220270 - Hardware Design Guide for the Traveo II Family

AN220191 - How to use direct memory access (DMA) controller in TRAVEO™ II family

AN220152 - How to Retain RAM Data in Reset Procedure and Low-Power Mode Transition in Traveo II Family

AN224454 - Using the SMIF in TRAVEO™ II family

AN226043 - How to Use Sound Subsystem in Traveo II Family

AN219843 - Protection Configuration in Traveo II

AN224432 - Multi Core Handling Guide in Traveo II

AN227076 - TRAVEO II BOOTLOADER

AN228104 - HOW TO USE TRIGGER MULTIPLEXER IN TRAVEO II FAMILY

AN224413 - HOW TO USE I2S IN TRAVEO II FAMILY

AN224434 - CLOCK CONFIGURATION SETUP IN TRAVEO II FAMILY CYT4B SERIES

AN224414 - USING SDHC HOST CONTROLLER IN TRAVEO II FAMILY MCU

AN224283 - HOW TO USE CXPI CONTROLLER IN TRAVEO II FAMILY

AN224619 - HOW TO USE ETHERNET CONTROLLER IN TRAVEO II FAMILY

AN219755 - Using a SAR ADC in Traveo II Family

AN229058 - Secure Firmware Over-The-Air (FOTA) Update in Traveo II

AN228680 - Secure System Configuration in Traveo II Family

AN218629 - Comparison of Traveo and Traveo II

AN219944 - Using the Watchdog Timer in Traveo II Family MCUs

AN220253 - Using the CRYPTO Module in Traveo II Family

AN220268 - HOW TO CONTROL MOTOR IN TRAVEO II FAMILY

AN220278 - HOW TO USE CAN FD IN TRAVEO II FAMILY

AN220203 - SMART I/O USAGE SETUP IN TRAVEO II FAMILY

AN220222 - LOW POWER MODE PROCEDURE IN TRAVEO II FAMILY

AN220193 - GPIO USAGE SETUP IN TRAVEO II FAMILY

AN225346 - Using the LIN in Traveo II Family

AN220224 - How to Use Timer, Counter, and PWM (TCPWM) in Traveo II Family

AN226037 - FPD-Link PCB Guidelines for the Traveo II Family CYT4D Series MCUs

AN219842 - How to Use Interrupt in Traveo II

AN226698 - External Power Supply Design Guide for Traveo II Family

AN220118 - GETTING STARTED WITH TRAVEO II FAMILY MCUS

AN220208 - Clock Configuration Setup in Traveo II Body Entry Family

TRAVEO™ T2G Trainings