OptiMOS™ 6 power MOSFETs in 40 V

Infineon's first product family of OptiMOS™ generation 6, cutting edge MOSFETs available in logic and normal level

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Overview

The OptiMOS™ 6 family of 40 V devices set a new technology standard for discrete power MOSFETs. With the OptiMOS™ 6 40 V logic level product family, Infineon offers a benchmark solution for applications requiring lower gate drive capability.

Key Features

  • Ultra-low Qg for low switching loss
  • Low RDS(on)
  • Low parasitics
  • Logic and normal gate drive
  • Superior thermal resistance

Products

About

Infineon's next generation of cutting-edge MOSFETs

Improvements in on-state resistance (RDS(on)) and figure of merit (FOM - RDS(on) x Qg and Qgd) enable designers to increase efficiency, allowing easier thermal design and less paralleling, leading to system cost reduction.

Infineon’s market-leading OptiMOS™ 6 power MOSFETs in 40 V are available in two different packages:

  • SuperSO8 – 5x6 mm with RDS(on) ranging from 5.9 mΩ down to 0.7 mΩ
  • PQFN 3x3 – 3.3x3.3 mm with RDS(on) ranging from 6.3 mΩ down to 1.8 mΩ
OptiMOS™ 6 40 V combine best-in-class RDS(on) and superior switching

In SMPS applications, OptiMOS™ 6 is the perfect solution for optimizing efficiency over a wide range of output power, avoiding the trade-off between low and high load conditions.

At the low output power range, the switching losses dominate the efficiency curve. OptiMOS™ 6 power MOSFETs achieve better efficiency when compared to the same RDS(on) OptiMOS™ 5 because of its superior switching performance.

Moreover, at a higher output power, where the RDS(on) losses are dominant, OptiMOS™ 6 leads to better performance throughout the whole operating range.

Normal level MOSFETs with induced turn-on immunity

OptiMOS™ 6 power MOSFETs in normal level MOSFETs are optimized for immunity against unwanted induced turn-on, which often occurs in real-life applications and causes increased power dissipation leading to overheating and failure in extreme cases of end-equipment.

The mechanism of induced turn-on involves a high drain-to-source dV/dt inducing a voltage spike at the gate because of the capacitive voltage divider formed by the gate-to-drain (Miller) and gate-to-source capacitances. This can be quantified as a charge ratio Qgd/Qgs.

For logic-level devices, the gate threshold voltage (Vth) is typically below 2 V. With induced voltage spikes on the gate, the MOSFET will turn on. A higher Vth for the normal level portfolio means that only larger gate voltage spikes would cause unwanted turn-on.

In addition, lower Qgd/Qgs ratios (Cgd/Cgs divider ratio) reduce the peak of the gate voltage spikes, further contributing to the robustness against unwanted turn-on. With the normal level device, additional design margin at elevated temperatures is available, as Vth decreases with rising temperatures.

Infineon's next generation of cutting-edge MOSFETs

Improvements in on-state resistance (RDS(on)) and figure of merit (FOM - RDS(on) x Qg and Qgd) enable designers to increase efficiency, allowing easier thermal design and less paralleling, leading to system cost reduction.

Infineon’s market-leading OptiMOS™ 6 power MOSFETs in 40 V are available in two different packages:

  • SuperSO8 – 5x6 mm with RDS(on) ranging from 5.9 mΩ down to 0.7 mΩ
  • PQFN 3x3 – 3.3x3.3 mm with RDS(on) ranging from 6.3 mΩ down to 1.8 mΩ

OptiMOS™ 6 40 V combine best-in-class RDS(on) and superior switching

In SMPS applications, OptiMOS™ 6 is the perfect solution for optimizing efficiency over a wide range of output power, avoiding the trade-off between low and high load conditions.

At the low output power range, the switching losses dominate the efficiency curve. OptiMOS™ 6 power MOSFETs achieve better efficiency when compared to the same RDS(on) OptiMOS™ 5 because of its superior switching performance.

Moreover, at a higher output power, where the RDS(on) losses are dominant, OptiMOS™ 6 leads to better performance throughout the whole operating range.

Normal level MOSFETs with induced turn-on immunity

OptiMOS™ 6 power MOSFETs in normal level MOSFETs are optimized for immunity against unwanted induced turn-on, which often occurs in real-life applications and causes increased power dissipation leading to overheating and failure in extreme cases of end-equipment.

The mechanism of induced turn-on involves a high drain-to-source dV/dt inducing a voltage spike at the gate because of the capacitive voltage divider formed by the gate-to-drain (Miller) and gate-to-source capacitances. This can be quantified as a charge ratio Qgd/Qgs.

For logic-level devices, the gate threshold voltage (Vth) is typically below 2 V. With induced voltage spikes on the gate, the MOSFET will turn on. A higher Vth for the normal level portfolio means that only larger gate voltage spikes would cause unwanted turn-on.

In addition, lower Qgd/Qgs ratios (Cgd/Cgs divider ratio) reduce the peak of the gate voltage spikes, further contributing to the robustness against unwanted turn-on. With the normal level device, additional design margin at elevated temperatures is available, as Vth decreases with rising temperatures.

Documents

Documents

Design resources

Developer community

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