Active and preferred
RoHS Compliant
Lead-free

IPDQ65R080CFD7A

650 V CoolMOS™ CFD7A N-channel automotive SJ power MOSFET in HDSOP-22 top-side cooling
Data Sheet
package
ea.
in stock

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IPDQ65R080CFD7A
IPDQ65R080CFD7A
ea.
Data Sheet

Product details

  • ID (@25°C) max
    36 A
  • ID max
    36 A
  • IDpuls max
    107 A
  • Mounting
    SMT
  • Operating Temperature
    -55 °C to 150 °C
  • Package
    Q-DPAK
  • Polarity
    N
  • Ptot max
    223 W
  • QG (typ @10V)
    50 nC
  • QG
    50 nC
  • Qualification
    Automotive
  • RDS (on) (@ Tj = 25°C)
    66 mΩ
  • Special Features
    Highest cosmic radiation robustness
  • Technology
    CoolMOS™ CFD7A
  • VDS max
    650 V
  • VGS(th)
    4 V
Recommended
OPN
IPDQ65R080CFD7AXTMA1
Product Status active and preferred
Infineon Package
PG-HDSOP-22
Package Name Q-DPAK
Packing Size 750
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-HDSOP-22
Package Name Q-DPAK
Packing Size 750
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The 80mΩ IPDQ65R080CFD7A in QDPAK top side cooling SMD package is part of the automotive-qualified 650 V CoolMOS™ SJ power MOSFET CFD7A product family. As compared to the previous generation, CoolMOS™ CFD7A offers higher reliability and power density while increasing design flexibility. Top side cooling further supports increased power density, reduces parasitic source inductance and comes with Kelvin source pin and3.2 mm creepage distance.

Features

  • AEC-Q101 qualified
  • For hard- and soft-switching topologies
  • Intrinsic fast body diode
  • Reduced parasitic source inductance
  • Kelvin source pin
  • High current capability
  • High power dissipation, Ptot 694 W/25°C
  • Creepage distance of 3.2 mm for HV

Benefits

  • Better utilization of PCB space
  • Highest reliability for automotive appl.
  • Optimized power loop
  • Decoupling of thermals from substrate
  • Enabling of higher power density designs
  • Scalable for use in PFC and DC-DC stage
  • Granular portfolio available

Documents

Documents

Design resources

Partner solutions

Developer community

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