In high-performance space computing, data buffering demands exceed on-chip memory capacity in MCUs or FPGAs. System designers need higher-performing memory to meet the real-time processing demands of applications. Since radiation effects and technology defect density can cause unavoidable bit errors in SRAMs, superior radiation performance is also essential to meet mission requirements.

Available in 8-, 16- and 32-bit wide configurations, Infineon’s new rad hard SRAMs offer embedded error correction code (ECC) for single-bit error correction. This advanced technology enables the ECC logic to detect and correct single-bit errors in any read data word during the read cycles.

The new async SRAMs are designed with Infineon’s patented RADSTOP™ technology which meets all radiation requirements for extreme environments.

  • Technology FIT rate 1000x more reliable than standard SRAMs without ECC
  • Embedded single error correction (SEC) failure rates less than 1e-10 error/bit-day
  • Single-chip solution with on-chip ECC reduces board space, cost and design complexity and delivers high performance with 10ns access time