Asynchronous SRAM

Asynchronous SRAMs offer high-speed, low-power expansion memory with on-chip ECC to suit automotive and industrial applications

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Overview

Asynchronous SRAMs are used as expansion memory in automotive and industrial applications due to its high reliability and long-term support. Micropower asynchronous SRAMs are used for data logging in battery-powered and battery-backed solutions (BBSRAM) across a range of applications. Infineon’s asynchronous SRAMs are QML certified for defense products and available in TSOP, BGA, and SOP packages.

Key Features

  • Fast access time of 10 ns
  • Low-pwr consumption - PowerSnooze™
  • High reliability <0.1 FIT/Mbit
  • Long-term support commitment
  • RoHS compliant
  • QML certified

Products

About

High speed, low power with on-chip ECC to suit myriad applications

Asynchronous SRAM is a type of volatile random-access memory (RAM) that uses flip-flop based latching circuitry to store each bit. The data bits are retained in memory as long as power is supplied. Infineon provides the industry’s broadest portfolio of asynchronous SRAMs from 256 KB to 64 MB. Asynchronous SRAMs are used in networking, defense, and industrial applications due to its high reliability and long-term support offered. MoBL™ asynchronous SRAMs are also ideal for battery-powered and battery-backed solutions (BBSRAM) across a range of application segments that require data backup on power loss.

Infineon’s asynchronous SRAMs are RoHS compliant, QML certified for defense products and available in industry standard TSOP, BGA, SOP packages.

  • Density: 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, and 64 MB
  • Interface: I2C, SPI, QSPI, and parallel (x8, x16, x32)
Provides the industry's broadest portfolio of asynchronous SRAM memory

Our asynchronous fast SRAMs are industry’s fastest parallel asynchronous SRAM solutions with fastest access time of 10 ns. These are available in densities ranging from 64 Kbit – 32 Mbit and supports wide voltage range from 1.8 V to 5 V. These are used in networking applications such as switches and routers.

Our Async Micropower (MOBL™) SRAMs are the most energy-efficient asynchronous SRAM solutions with PowerSnooze™ mode. These are available in densities ranging from 256 Kbit – 64 Mbit and supports wide voltage range from 1.8 V to 5 V. These are used in battery-powered and battery-backed solutions.

Combine fast access time with a unique ultra-low-power sleep mode

Infineon’s asynchronous SRAM memories combine the access time of fast asynchronous SRAM with a unique ultra-low-power sleep mode into one chip through the PowerSnooze™ feature. This feature lets SRAMs operate at fast speeds of 10 ns (100 MHz), while consuming < 2 µA / Mbit (typ.) of sleep current. By invoking this “deep sleep” feature, SRAMs' quickly transition from a high-speed active state to a power-saving sleep state. This ensures that the full power of your MCU is harnessed, since the SRAM is no longer the limitation to achieving your peak performance. Read this application note to learn more about the feature.

Reliably-run, mission-critical applications without system errors

Systems running mission-critical applications need memories with zero system errors. Higher energy and extra-terrestrial radiations such as alpha particles, thermal neutrons, cosmic rays can flip multiple adjacent bits, leading to multi-bit errors.

Our asynchronous SRAMs use (38, 32) hamming code ECC for single-bit error detection, correction, and performs all ECC related functions in line, without user intervention. SRAMs with ECC are form-fit-function compatible with older generation asynchronous SRAMs. This allows you to improve system reliability without investing in PCB redesign.

Improve performance with multi-bit interleaving technology

A multi-bit upset is a type of radiation-induced upset identified when two or more flipped bits are physically adjacent or have a separation of, at most, one non-failing bit. Bit-interleave distance separates two consecutive bits mapped to the same word register. In a bit-interleaved memory, a single-bit error correction algorithm can be used to detect and correct all errors. Together, these features provide significant improvement in Soft Error Rate (SER) performance, resulting in industry’s most reliable SRAMs with <0.1 FIT/Mbit.

Ensure all data is securely backed up in the event of power failures

Battery-Backed SRAM's (BBSRAM's), also called NVRAM's are used in applications that require any kind of data backup in the event of a power failure. In these cases, we can use a conventional SRAM memory along with a back-up battery and control circuitry to create a fast, non-volatile memory. Infineon also offers FRAM and nvSRAM non-volatile memories for applications requiring higher endurance and longer retention.

Read this application note to understand the design considerations that need to be considered for using asynchronous SRAM in battery-backed applications.

High speed, low power with on-chip ECC to suit myriad applications

Asynchronous SRAM is a type of volatile random-access memory (RAM) that uses flip-flop based latching circuitry to store each bit. The data bits are retained in memory as long as power is supplied. Infineon provides the industry’s broadest portfolio of asynchronous SRAMs from 256 KB to 64 MB. Asynchronous SRAMs are used in networking, defense, and industrial applications due to its high reliability and long-term support offered. MoBL™ asynchronous SRAMs are also ideal for battery-powered and battery-backed solutions (BBSRAM) across a range of application segments that require data backup on power loss.

Infineon’s asynchronous SRAMs are RoHS compliant, QML certified for defense products and available in industry standard TSOP, BGA, SOP packages.

  • Density: 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, and 64 MB
  • Interface: I2C, SPI, QSPI, and parallel (x8, x16, x32)

Provides the industry's broadest portfolio of asynchronous SRAM memory

Our asynchronous fast SRAMs are industry’s fastest parallel asynchronous SRAM solutions with fastest access time of 10 ns. These are available in densities ranging from 64 Kbit – 32 Mbit and supports wide voltage range from 1.8 V to 5 V. These are used in networking applications such as switches and routers.

Our Async Micropower (MOBL™) SRAMs are the most energy-efficient asynchronous SRAM solutions with PowerSnooze™ mode. These are available in densities ranging from 256 Kbit – 64 Mbit and supports wide voltage range from 1.8 V to 5 V. These are used in battery-powered and battery-backed solutions.

Combine fast access time with a unique ultra-low-power sleep mode

Infineon’s asynchronous SRAM memories combine the access time of fast asynchronous SRAM with a unique ultra-low-power sleep mode into one chip through the PowerSnooze™ feature. This feature lets SRAMs operate at fast speeds of 10 ns (100 MHz), while consuming < 2 µA / Mbit (typ.) of sleep current. By invoking this “deep sleep” feature, SRAMs' quickly transition from a high-speed active state to a power-saving sleep state. This ensures that the full power of your MCU is harnessed, since the SRAM is no longer the limitation to achieving your peak performance. Read this application note to learn more about the feature.

Reliably-run, mission-critical applications without system errors

Systems running mission-critical applications need memories with zero system errors. Higher energy and extra-terrestrial radiations such as alpha particles, thermal neutrons, cosmic rays can flip multiple adjacent bits, leading to multi-bit errors.

Our asynchronous SRAMs use (38, 32) hamming code ECC for single-bit error detection, correction, and performs all ECC related functions in line, without user intervention. SRAMs with ECC are form-fit-function compatible with older generation asynchronous SRAMs. This allows you to improve system reliability without investing in PCB redesign.

Improve performance with multi-bit interleaving technology

A multi-bit upset is a type of radiation-induced upset identified when two or more flipped bits are physically adjacent or have a separation of, at most, one non-failing bit. Bit-interleave distance separates two consecutive bits mapped to the same word register. In a bit-interleaved memory, a single-bit error correction algorithm can be used to detect and correct all errors. Together, these features provide significant improvement in Soft Error Rate (SER) performance, resulting in industry’s most reliable SRAMs with <0.1 FIT/Mbit.

Ensure all data is securely backed up in the event of power failures

Battery-Backed SRAM's (BBSRAM's), also called NVRAM's are used in applications that require any kind of data backup in the event of a power failure. In these cases, we can use a conventional SRAM memory along with a back-up battery and control circuitry to create a fast, non-volatile memory. Infineon also offers FRAM and nvSRAM non-volatile memories for applications requiring higher endurance and longer retention.

Read this application note to understand the design considerations that need to be considered for using asynchronous SRAM in battery-backed applications.

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