S70KL1281DABHI023

High-Performance 128 MBit HYPERRAM with 40ns Initial Access Time and 200 MByte/s Interface Bandwidth
Data Sheet

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S70KL1281DABHI023
S70KL1281DABHI023
Data Sheet

Product details

  • Density
    128 MBit
  • Family
    KL-1
  • Initial Access Time
    40 ns
  • Interface Bandwidth
    200 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 100
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    N/A
  • Operating Temperature
    -40 °C to 85 °C
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Technology
    HYPERRAM
OPN
Product Status
Infineon Package
Package Name
Packing Size
Packing Type
Moisture Level
Moisture Packing
Lead-free
Halogen Free
RoHS Compliant
Infineon stock last updated:
The Cypress® HyperRAM™ device is a high-speed CMOS DRAM with a HyperBus interface. The 128 Mb version is a dual-die stack of 64 Mb devices. With refresh control logic, it resembles PSRAM to the host, eliminating the need for manual refresh operations. The host should manage transaction duration to accommodate internal refresh needs.

Features

  • 3.0 V I/O, 11 bus signals:Single ended clock (CK)
  • 1.8 V I/O, 12 bus signals: Differential clock (CK, CK#)
  • Chip Select (CS#)
  • 8-bit data bus (DQ[7:0])
  • Read-Write Data Strobe (RWDS)
  • RWDS DCARS Timing
  • Double-Data Rate (DDR)
  • 100 MHz clock rate (200 MBps) at 3.0 V VCC
  • Sequential burst transactions 
  • Configurable Burst Characteristics

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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