coming soon
RoHS Compliant
Lead-free

2EDR3142XQE

5.7 kV (rms) dual-channel gate driver IC with AEC-Q100 qualification, reinforced isolation, 6.5 A output current, 4.8 V UVLO
Data Sheet

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2EDR3142XQE
2EDR3142XQE
Data Sheet

Product details

  • Channels
    2
  • Configuration
    High-side
  • Input Vcc
    -0.3 V to 17 V
  • Isolation Type
    Galvanic isolation - Reinforced
  • Output Current (Source)
    6 A
  • Output Current (Sink)
    6.5 A
  • Package
    PG-DSO-14-79
  • Product Name
    2EDR3142XQE
  • Qualification
    AEC-Q100
  • Turn Off Propagation Delay
    39 ns
  • Turn On Propagation Delay
    39 ns
  • VBS UVLO (Off)
    4.8 V
  • VBS UVLO (On)
    5.2 V
  • Voltage Class
    2300 V
OPN
2EDR3142XQEXUMA1
Product Status coming soon
Infineon Package PG-DSO-14
Package Name N/A
Packing Size 1500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status coming soon
Infineon Package PG-DSO-14
Package Name -
Packing Size 1500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
EiceDRIVER™ Compact 2300 V dual-channel isolated gate driver with +/-6.5 A typical peak output current in a 14-pin DSO wide body package for GaN HEMTs, IGBTs, MOSFETs and SiC MOSFETs. Qualified according to AEC-Q100. Offers dead-time control (DTC) and independent channel operation, allowing for operation as a dual-channel low-side driver, a dual-channel high-side driver, or a half-bridge gate driver with a configurable dead-time.

Features

  • For up to 2300 V Switches
  • 2300 V input-output functional isolation
  • Galvanically isolated coreless xformer
  • 35 V abs. max. output supply voltage
  • Up to 17 V input supply voltage
  • 39 ns typ propogation delay
  • 5.2 V / 4.8 V UVLO protection
  • CTI 600 Package with 8 mm creepage
  • Enable Pin
  • Product validation according to AEC-Q100

Benefits

  • Strong 6.5 A output stage
  • Best-in-class CMTI of > 200 kV/µs
  • 8 mm input-to-output
  • 3.3 mm ch-to-ch
  • Part-to-part prop delay skew+ of 8 ns max
  • Ch-to-ch prop delay skew of 5ns max
  • IEC 60747-17 (planned), UL 1577
  • VIORM = 1767 V (peak, reinforced)
  • VISO = 5.7 kV (rms) for 1 min
  • UVLO options for GaN, Si, IGBT, SiC
  • Pin-to-pin package option

Documents

Documents

Design resources

Partner solutions

Developer community

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