Filter

Streamline Your Filtering Needs with the Versatile Filter Component

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About

The Filter component allows easy creation of single or dual channel digital filters using the DFB. The component includes a filter design feature, which greatly simplifies the design and implementation processes. It supports two streaming channels that can be streamed directly from other hardware blocks (such as the ADC) using DMA. The filtered results can likewise be transferred using DMA, interrupts, or polling methods. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels, and this information is used to guide the choice of filter implementation. It reports (but does not set) the minimum bus clock frequency required to execute the filtering within the declared sample interval. This clock can then be set in the design-wide resource manager.

The Filter component supports many use cases. If something unusual occurs when using it, please report it (with a good description). Contact tech support at

Streamline filter configuration with the Digital Filter Block (DFB) in select PSOC™ 3 and PSOC™ 5 LP devices, featuring support for two separate filter channels, each constructed with a cascade of up to four separately designed stages. Enjoy multiple FIR and IIR (Biquad) filter methods, flexible coefficient entry, and access to final coefficient values for in-depth analysis.

The Filter component allows easy creation of single or dual channel digital filters using the DFB. The component includes a filter design feature, which greatly simplifies the design and implementation processes. It supports two streaming channels that can be streamed directly from other hardware blocks (such as the ADC) using DMA. The filtered results can likewise be transferred using DMA, interrupts, or polling methods. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels, and this information is used to guide the choice of filter implementation. It reports (but does not set) the minimum bus clock frequency required to execute the filtering within the declared sample interval. This clock can then be set in the design-wide resource manager.

The Filter component supports many use cases. If something unusual occurs when using it, please report it (with a good description). Contact tech support at

Streamline filter configuration with the Digital Filter Block (DFB) in select PSOC™ 3 and PSOC™ 5 LP devices, featuring support for two separate filter channels, each constructed with a cascade of up to four separately designed stages. Enjoy multiple FIR and IIR (Biquad) filter methods, flexible coefficient entry, and access to final coefficient values for in-depth analysis.

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Design resources