External Memory Interface (EMIF)

Revolutionary EMIF Component Simplifies CPU and DMA Access to External Memory ICs for PSoC™ 3/PSoC™ 5LP

About

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC™ 3/PSoC™ 5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

This versatile component offers a wide range of features, including support for 8-, 16-, and 24-bit address bus widths, 8- and 16-bit data bus widths, compatibility with both external synchronous and asynchronous memory, a customizable memory interface, the ability to work with external memories at speeds ranging from 5 to 200 ns, and support for external memory power-down, sleep, and wakeup modes.

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC™ 3/PSoC™ 5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

This versatile component offers a wide range of features, including support for 8-, 16-, and 24-bit address bus widths, 8- and 16-bit data bus widths, compatibility with both external synchronous and asynchronous memory, a customizable memory interface, the ability to work with external memories at speeds ranging from 5 to 200 ns, and support for external memory power-down, sleep, and wakeup modes.

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Design resources