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AURIX™ Safety sets the industry standard, leveraging advanced microcontroller technology to deliver unparalleled safety and reliability across diverse automotive and industrial applications

Explore our partner offerings in the Design resources and Partners space below:

  • Set of SW tests to support applications with functional safety requirements including “Software-Based Self Test” (SBST) for the CPU core
  • Support of system integration with application-dependent tests
  • Handling of internal and external watchdogs (SafeWDG)

SBST for non LS CPU – supporting ASIL-B

  • The CPU Software Based Self Test (SBST) is a safety mechanism that supports the ISO26262 SPFM for ASIL B safety goals. The SBST detects Permanent Random Hardware Faults in the fetch unit and pipelines of non-lockstep CPU cores with a diagnostic coverage level of 90%.
  • Required for applicants with an ASIL B requirement on AURIX™ TC3xx non-lockstep CPUs.

 

SBST for SPU – supporting ADAS cluster ASIL-C applications

  • The SPU Software Based Self Test (SBST) is a safety mechanism that supports the ISO26262 SPFM and is similar in concept to the CPU SBST described above.
To support you during the evaluation of your product/board, Infineon Developer Center provides you with projects section, where you can register your infineon Boards in order to get access to all exclusive content

AURIX™ Safety sets the industry standard, leveraging advanced microcontroller technology to deliver unparalleled safety and reliability across diverse automotive and industrial applications

Explore our partner offerings in the Design resources and Partners space below:

  • Set of SW tests to support applications with functional safety requirements including “Software-Based Self Test” (SBST) for the CPU core
  • Support of system integration with application-dependent tests
  • Handling of internal and external watchdogs (SafeWDG)

SBST for non LS CPU – supporting ASIL-B

  • The CPU Software Based Self Test (SBST) is a safety mechanism that supports the ISO26262 SPFM for ASIL B safety goals. The SBST detects Permanent Random Hardware Faults in the fetch unit and pipelines of non-lockstep CPU cores with a diagnostic coverage level of 90%.
  • Required for applicants with an ASIL B requirement on AURIX™ TC3xx non-lockstep CPUs.

 

SBST for SPU – supporting ADAS cluster ASIL-C applications

  • The SPU Software Based Self Test (SBST) is a safety mechanism that supports the ISO26262 SPFM and is similar in concept to the CPU SBST described above.

To support you during the evaluation of your product/board, Infineon Developer Center provides you with projects section, where you can register your infineon Boards in order to get access to all exclusive content

Documents

Design resources