CYPRESS™ Buffers

High-performance buffers offer low-jitter and programmable skew buffers

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Overview

Infineon's high-performance buffers (CY2Dx/CY2Cx series) are a family of low-jitter, non-PLL fanout buffers that deliver up to ten high-frequency differential outputs (LVPECL, LVDS, or CML) up to 1.5 GHz. They deliver the industry’s lowest additive jitter (0.06 ps, typical) and can provide complete high-frequency, low-jitter clock tree solutions in conjunction with CY294x/CY274x parts.

Key Features

  • Programmable output skew
  • Programmable multiplier/divider
  • Redundant fault-tolerant clocks
  • High-frequency outputs

Products

About

Infineon's buffer portfolio
  • Non-Zero Delay Buffers (NZDB) - A Non-zero delay buffer is a device that can fan out one clock signal into multiple clock signals with propagation delay as it has no PLL.
  • Zero Delay Buffers (ZDB) - A zero delay buffer is a device with PLL that can fan out one clock signal into multiple clock signals with no delay and low skew between the outputs.
Learn more about buffers here
Infineon's buffers used in variety of applications

The on-resistance (RDS(on)) can be drastically reduced by a factor of four or more per package type, compared to other 900 V conventional MOSFETs. 900 V CoolMOS™ C3 also offers a very low figure-of-merit on-resistance times gate charge (RDS(on)*Qg) of 34W*nC, translating into low conduction, driving, and switching losses. The energy stored in the output capacitance is reduced by a factor of two compared to conventional 900 V MOSFETs, which reduces power losses during hard-switched turn-on.

High performance buffer advantages

• Ultra-low additive jitter improves the system timing margin for high-performance applications

• Fast signal rise/fall times meet the latest high-speed interface requirements

• Low output-output skew ensures predictable timing relationships of output signals

Infineon's buffer portfolio
  • Non-Zero Delay Buffers (NZDB) - A Non-zero delay buffer is a device that can fan out one clock signal into multiple clock signals with propagation delay as it has no PLL.
  • Zero Delay Buffers (ZDB) - A zero delay buffer is a device with PLL that can fan out one clock signal into multiple clock signals with no delay and low skew between the outputs.
Learn more about buffers here

Infineon's buffers used in variety of applications

The on-resistance (RDS(on)) can be drastically reduced by a factor of four or more per package type, compared to other 900 V conventional MOSFETs. 900 V CoolMOS™ C3 also offers a very low figure-of-merit on-resistance times gate charge (RDS(on)*Qg) of 34W*nC, translating into low conduction, driving, and switching losses. The energy stored in the output capacitance is reduced by a factor of two compared to conventional 900 V MOSFETs, which reduces power losses during hard-switched turn-on.

High performance buffer advantages

• Ultra-low additive jitter improves the system timing margin for high-performance applications

• Fast signal rise/fall times meet the latest high-speed interface requirements

• Low output-output skew ensures predictable timing relationships of output signals

Documents

Documents

Design resources

Developer community

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