Active and preferred
RoHS Compliant

IQE022N06LM5CG

OptiMOS™ 5 power MOSFET 60 V logic level in PQFN 3.3x3.3 Source-Down Center-Gate package
Data Sheet
package
ea.
in stock

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IQE022N06LM5CG
IQE022N06LM5CG
ea.
Data Sheet

Product details

  • Budgetary Price €/1k
    1.01
  • ID (@25°C) max
    151 A
  • IDpuls max
    604 A
  • Operating Temperature
    -55 °C to 175 °C
  • Package
    PQFN 3.3x3.3 Source-Down
  • Polarity
    N
  • Ptot max
    100 W
  • QG (typ @4.5V)
    26 nC
  • QG (typ @10V)
    53 nC
  • RDS (on) (@4.5V) max
    2.9 mΩ
  • RDS (on) (@10V) max
    2.2 mΩ
  • Special Features
    Center-Gate
  • VDS max
    60 V
  • VGS(th)
    1.7 V
Recommended
OPN
IQE022N06LM5CGATMA1
Product Status active and preferred
Infineon Package
PG-TTFN-9
Package Name PQFN 3.3x3.3 Source-Down DSC
Packing Size 5000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TTFN-9
Package Name PQFN 3.3x3.3 Source-Down DSC
Packing Size 5000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
IQE022N06LM5CG is Infineon’s new best-in-class OptiMOS™ 5 Power MOSFET 60 V logic level in PQFN 3.3x3.3 Source-Down Center-Gate (CG) package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C, superior thermal performance, and optimized parallelization. The OptiMOS™ Source-Down is a revolutionary technology with a flipped silicon die inside, offering several advantages such as better thermal capability, higher power density and improved layout possibilities. Combined with the new PQFN 3.3x3.3 Center-Gate package, IQE022N06LM5CG is targeted for high power density and performance SMPS products commonly found in telecom and data servers.

Features

  • Logic level allows lower Qrr
  • Reduced RDS(on)by up to 30%
  • Reduced RthJC vs. existing PQFN
  • Center Gate optimized for paralleling

Benefits

  • Enabling highest power density
  • Superior thermal performance
  • Efficient layout for space use
  • Simplified MOSFET parallelization

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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