Active and preferred
RoHS Compliant
Lead-free

SAK-TC277TF-64F200N DC

Debug, Trave, Measure and Calibrate

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SAK-TC277TF-64F200N DC
SAK-TC277TF-64F200N DC

Product details

  • # of cores / lockstep cores
    3/2
  • A/D Input Lines (incl. FADC)
    60
  • ASIL/SIL support
    ASIL-D/SIL-3
  • CAN Nodes
    5
  • Classification
    ISO 26262-compliant
  • DMA Channels
    64
  • DSP Functionality
    yes
  • eMMC
    no
  • External Bus Interface
    no
  • Family
    AURIX™ 1G
  • Floating Point Unit
    yes
  • Hardware Accelerator
    no
  • I/O Operation Voltages
    3.3 V to 5 V
  • LIN
    4
  • Number of ADC Modules
    14
  • On-chip Clock Generation
    yes
  • On-chip Voltage Regulator
    yes
  • Oscillator Watchdog
    yes
  • Program Memory
    4 MByte
  • Real Time Clock
    yes
  • SPI
    4
  • SRAM (incl. Cache)
    472 kByte
  • Temperature
    -40°C - +125°C
  • Type of Memory
    Flash
  • Watchdog Timer
    yes
OPN
TC277TF64F200NDCKXUMA1
Product Status active and preferred
Infineon Package
Package Name N/A
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
Package Name -
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
SAK-TC277TF-64F200N DC belongs to the TC2x Emulation Devices , . It has the same feature set as the TC27x standard family with additional debug and tracing capabilities. SAK-TC277TF-64F200N DC offers support for calibration, rapid prototyping, instrumentation and debug/emulation.

Features

  • Devices:3 TriCore™ running at 200 MHz
  • 4 MB flash with ECC protection
  • 472 KB SRAM with ECC protection
  • Sensor interfaces:10xSENT,3xPSI5,1xPSI5S
  • Connectivity :1xEthernet 100 Mbit
  • PG-LFBGA-292
  • Single voltage supply 3.3 V or 5 V
  • Temperature : 40°C to 125°C
  • Emulation Features 2 MB Extension Memory
  • Multi-Core Debug Solution (MCDS)
  • Parallel & time aligned trace of cores
  • Powerful trigger conditions

Documents

Design resources

Developer community

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