Active and preferred
RoHS Compliant

IQE006NE2LM5SC

OptiMOS™ low-voltage power MOSFET 25 V in PQFN 3.3x3.3 Source-Down DSC package with industry leading RDS(on) and superior thermal performance
ea.
in stock

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IQE006NE2LM5SC
IQE006NE2LM5SC
ea.

Product details

  • Budgetary Price €/1k
    0.8
  • ID (@25°C) max
    310 A
  • ID max
    310 A
  • IDpuls max
    1240 A
  • Operating Temperature
    -55 °C to 150 °C
  • Package
    PQFN 3.3x3.3 Source-Down
  • Polarity
    N
  • Ptot max
    89 W
  • QG (typ @10V)
    62 nC
  • QG (typ @4.5V)
    29 nC
  • RDS (on) (@10V) max
    0.58 mΩ
  • RDS (on) (@4.5V) max
    0.75 mΩ
  • Special Features
    Dual-Side Cooling
  • VDS max
    25 V
  • VGS(th)
    1.6 V
OPN
IQE006NE2LM5SCATMA1
Product Status active and preferred
Infineon Package
Package Name PQFN 3.3x3.3 Source-Down DSC
Packing Size 6000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
ea. in stock

Product Status
Active
Infineon Package
Package Name PQFN 3.3x3.3 Source-Down DSC
Packing Size 6000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
OptiMOS™5 25 V PQFN 3.3x3.3 Source-Down DSC: offering a flipped silicon die, which is positioned upside down inside of the components. This adjustment allows the source potential (instead of the drain potential) to be connected to the PCB over the thermal pad. Therefore, it offers several advantages, such as increased thermal capability, advanced power density or improved layout possibilities.

Features

  • Major reduction in RDS(on)30%
  • RthJCover current PQFN
  • Standard & Center Gate available
  • New, optimized layout possibilities

Benefits

  • Enabling highest power density
  • Superior thermal performance
  • Efficient layout for space use
  • Simplified MOSFET parallelization
  • Improved PCB losses
  • Reduced parasitics

Documents

Design resources

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }