Active and preferred
RoHS Compliant
Lead-free

S25FS128SDSNFM100

Data Sheet
package
software

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S25FS128SDSNFM100
S25FS128SDSNFM100
Data Sheet

Product details

  • Classification
    ISO 26262-ready
  • Density
    128 MBit
  • Family
    FS-S
  • Interface Bandwidth
    80 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / 80
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Matte Tin Plating
  • Operating Temperature
    -40 °C to 125 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Automotive
Recommended
OPN
S25FS128SDSNFM100
Product Status active and preferred
Infineon Package
PG-WSON-8
Package Name DFN-8 (002-18755)
Packing Size 980
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-WSON-8
Package Name DFN-8 (002-18755)
Packing Size 980
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S25FS128SDSNFM100 is a 128 Mbit (16 MB) SPI Multi-I/O NOR Flash memory operating from 1.7 V to 2.0 V, with DDR Quad I/O read speeds up to 80 MBps. It offers hybrid and uniform sector options, advanced sector protection, and automatic ECC for single-bit error correction. With 100,000 minimum program-erase cycles, 20-year data retention, and AEC-Q100 Grade 1 automotive qualification (-40°C to +125°C), it is ideal for industrial and automotive applications.

Features

  • Serial peripheral interface (SPI)
  • Double data rate (DDR) option
  • 24- or 32-bit address options
  • Multi I/O command support
  • Normal, Fast, Dual, Quad, DDR Quad I/O reads
  • Burst Wrap, Continuous (XIP), QPI modes
  • 256- or 512-byte page programming buffer
  • Automatic ECC, single-bit error correction
  • Hybrid and uniform sector erase options
  • 100,000 program-erase cycles minimum
  • 20 year data retention minimum
  • 1.7 V to 2.0 V supply voltage

Benefits

  • Flexible SPI supports many host controllers
  • DDR and Quad I/O enable high data rates
  • 32-bit addressing supports large designs
  • Multi I/O boosts read/write performance
  • Multiple read modes fit varied applications
  • XIP/QPI enable execute-in-place operation
  • Large page buffer speeds up programming
  • ECC improves data reliability
  • Flexible erase options ease partitioning
  • High endurance for long device lifetime
  • Long retention secures critical data
  • Low voltage reduces power consumption

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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