Active and preferred

CYPT2642KV18-250GCMB

Data Sheet
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CYPT2642KV18-250GCMB
CYPT2642KV18-250GCMB
Data Sheet

Product details

  • Architecture
    QDR-II+, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 18
  • Density
    144 MBit
  • Device weight
    6152.8 mg
  • ECC
    N
  • Family
    QDR-II+, ODT
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    Y
  • Operating Temperature
    -55 °C to 125 °C
  • Operating Voltage
    1.7 V to 1.9 V
  • Organization (X x Y)
    8Mb x 18
  • Peak Reflow Temp
    220 °C
  • Planned to be available until at least
    2033
  • Qualification
    Military
  • Read Latency (Cycles)
    2
  • Real Time Clock
    N
  • Watchdog
    N
Recommended
OPN
CYPT2642KV18-250GCMB
Product Status active and preferred
Infineon Package
C-CGA-165
Package Name CCGA-165 (001-58969)
Packing Size 1
Packing Type TRAY
Moisture Level 1
Moisture Packing NON DRY
Lead-free No
Halogen Free No
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
C-CGA-165
Package Name CCGA-165 (001-58969)
Packing Size 1
Packing Type TRAY
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
Infineon’s 144Mb Quad Data Rate (QDR®)-II+, CYRS164x and CYRS264x series, are high performance, synchronous pipelined SRAMs designed with Infineon’s RADSTOP™ technology.  The 144Mb QDR®-II+ memories are available in x18/x36 and two-word/four-word data bus configurations, and optional on-die termination (ODT).  Our QDR®-II+ provides low latency and random memory access capability ideal for high speed cache applications. Infineon’s radiation hardened memories are QML-V certified, meeting the reliability and lifecycle demands of extreme environments. Our RADSTOPTM memory solutions enhance overall system computing limits while providing Size, Weight, and Power (SWaP) benefits and greater design flexibility. Infineon’s state-of-the art RADSTOP™ technology is radiation hardened through proprietary design and process hardening techniques.

Features

  • 144 Mb density, 8M x 18 with two-word burst mode
  • 250MHz max frequency / 36 Gbps throughput
  • Two independent unidirectional data ports for concurrent r/w transactions
  • Double Data Rate (DDR) port
  • Output impedance matching input (ZQ) matches the device outputs to system data bus impedance
  • Memory core bit-interleaving to eliminate multi-bit errors
  • On-die termination (ODT)
  • 1.5 V to 1.8 V HSTL I/O signaling standards
  • 1.7 V to 1.9 V operating voltage range
  • –55°C to +125°C military temperature grade
  • 165-ball ceramic CGA (CCGA)
  • PROTOTYPE
  • For flight  devices, order QML-V part number 5962R1821401VXF
  • Controller RTL IP cores with embedded EDAC are available for Xilinx and Microchip FPGAs
Dev kit available, to learn more:  QDR®-II+ mezzanine board (P/N: CYDK-QDRII-NODT)

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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