Active and preferred
RoHS Compliant
Lead-free

CY7C4142KV13-106FCXC

High-Performance QDR-IV Parallel Interface Memory with 1066 MHz Frequency and On-Die Termination for Commercial Applications
Data Sheet
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CY7C4142KV13-106FCXC
CY7C4142KV13-106FCXC
Data Sheet

Product details

  • Architecture
    QDR-IV
  • Bank Switching
    Y
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    Y
  • Family
    QDR-IV
  • Frequency
    1066 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature
    0 °C to 70 °C
  • Operating Voltage
    1.26 V to 1.34 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    8
Recommended
OPN
CY7C4142KV13-106FCXC
Product Status active and preferred
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 300
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 300
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The QDR™-IV XP (Xtreme Performance) SRAM is a high-performance memory device optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports. These ports are equipped with DDR interfaces and designated as port A and port B respectively. Accesses to these two data ports are concurrent and independent of each other. Access to each port is through a common address bus running at DDR. The control signals are running at SDR and determine if a read or write should be performed.

Features

  • 144 Mbit density (8M × 18, 4M × 36)
  • Total Random Transaction Rate of 2132 MT/s
  • Maximum operating frequency of 1066 MHz
  • Read latency of 8.0 clock cycles
  • Write latency of 5.0 clock cycles
  • Eight-bank architecture enables 1 access per bank per cycle
  • Two-word burst on all accesses
  • Dual independent bidirectional data ports

Applications

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Documents

Design resources

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