MIL-PRF-38535 covers screening requirements that all parts are submitted to as well as Quality Conformance inspection consisting of one or more of Group A, B, C, D and E for acceptance of the design of the process and of the production lot.

MIL-PRF-38535 applies to microcircuits such as integrated circuits (IC).

For more information on MIL-PRF-38535 screening and quality conformance inspection, consult the DoD document or contact factory.

Certification: 1) Qualified Manufacturers List (QML) Certification for Classes Q/B & V/S Hermetic Packages with Radiation Hardness, and 2) Laboratory Suitability for MIL-STD-883 Test Methods.

Other non-QML IC’s: IR HiRel screens IC devices to IR HiRel’s Qualified IR List (QIRL) with S and B-level equivalent screenings. QIRL part numbers have SCS and SCB suffixes.

Note 1 - Stage 1 life test (1,000 hours @125C) is performed on each wafer lot as part of wafer lot acceptance. A sample of 5 die from each wafer (45 die minimum from each wafer lot) will be subjected to 1,000 hours life test, similar to element evaluation requirements in MIL-PRF-38534, Class K. The steady state life test is performed and applied for QCI coverage; both Group C (class level B devices) and QCI Group B5 (class level S devices).

Note 1 - Use of alternate SPC Test Method and process controls instead of 100% nondestructive bond pull. Destructive bond pull test is performed with SPC derived limits and inspection. One (1) device is pre-conditioning @ 300ºC for 1 hour to verify aging reliability of wire bonds.

Note 2 - COTS: Use ANSI/ASQC Z1.4 Attributes Tables, General Inspection Level II, Double Sample, 0.65% AQL. If sample is rejected, then perform 100% pre-cap inspection.

Note 3 - Use of alternate Temperature Cycle Test Method instead of 10 cycles (-65ºC to 150ºC). Temperature cycle is performed with 20 cycles (-55ºC to 150ºC).

Note 4 - PIND test may be performed in any sequence after temperature cycling test and prior to post burn-in (interim) electrical parameters test.

Note 5 - Serialization only applies to Class Level S devices.

Note 6 - Perform random sample inspection of lot.  For lot size < 500 pcs, inspect sample of 22(0) and for lot sizes ≥ 500 pcs, inspect sample of 45(0).  If one defective is found, apply double sample inspection (additional 22 or 45 pcs), and if more than 1 defective inspect entire lot.

ATE TM reference: 3003 -Delay measurements, 3004 -Transition time measurements, 3005 -Power supply current, 3006 -High level output voltage, 3009 -Input current, low level, 3010 -Input current, high level and 3021 -High impedance (off-state) high-level output leakage current.

Note 1 - Resistance to solvents testing required only on devices using inks as a marking medium. Testing for laser marked devices is performed in QCI Group D.

Note 1 - Not required for qualification or quality conformance inspections where group D inspection is being performed on samples from the same inspection lot.

Note 2 - Resistance to solvents testing required only on devices using inks as a marking medium. Testing for laser marked devices is performed in QCI Group D.

Note 3 – Stage 2 life test is performed at the packaged product level in QCI group B5 for Class S inspection lots.  A sample is submitted to 340 hours burn-in at 125ºC. Sample inspection for small lots will be 12 parts, and 22 parts for large lots. Small lots shall not exceed 1,000 parts. Group B5 life 1,000 hour life is not required to be performed on production lots when covered at Wafer Lot Acceptance (Stage 1) and all the following conditions are met:

(a) Subsequent production lots utilize die from the same wafer lot as the initial production lot.

(b) Wafers or die remaining from the initial production lot are to be stored in dry nitrogen or equivalent controlled storage, and

in covered containers.

(c) No major changes to the assembly processes have occurred since the group WLA (B5/C) test was performed on the wafer lot.

Note 1 – Group C life test (1,000 hour) is not required to be performed when covered at Wafer Lot Acceptance.

Screening Designators (PN suffix):

Wafer Lot Acceptance
Wafer Lot Acceptance
Wafer Lot Acceptance
radhardIC Nomeclature
radhardIC Nomeclature
radhardIC Nomeclature
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