Active
RoHS Compliant
Lead-free

IR2109S

600 V half-bridge gate driver IC with shutdown
Data Sheet
package
Multiple OPNs available
ea.

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IR2109S
IR2109S
ea.
Data Sheet

Product details

  • Channels
    2
  • Configuration
    Half Bridge
  • Input Vcc
    10 V to 20 V
  • Isolation Type
    Functional levelshift JI (Junction Isolated)
  • Output Current (Source)
    0.2 A
  • Output Current (Sink)
    0.35 A
  • Qualification
    Industrial
  • Turn Off Propagation Delay
    200 ns
  • Turn On Propagation Delay
    750 ns
  • VBS UVLO (On)
    8.9 V
  • VBS UVLO (Off)
    8.2 V
  • VCC UVLO (On)
    8.9 V
  • VCC UVLO (Off)
    8.2 V
  • Voltage Class
    600 V
Recommended
OPN
IR2109STRPBF IR2109SPBF
Product Status active not for new design
Infineon Package
SOIC 8N
SOIC 8N
Package Name N/A N/A
Packing Size 2500 3800
Packing Type TAPE & REEL TUBE
Moisture Level 2 2
Moisture Packing DRY DRY
Lead-free Yes Yes
Halogen Free Yes Yes
RoHS Compliant Yes Yes
Infineon stock last updated:
 ea. in stock ea. in stock

Product Status
Active
Infineon Package
SOIC 8N
Package Name -
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 2
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock

Product Status not for new design
Infineon Package
SOIC 8N
Package Name -
Packing Size 3800
Packing Type TUBE
Moisture Level 2
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
EiceDRIVER™ 600 V half bridge gate driver IC with typical 0.2 A source and 0.35 A sink currents in 8 Lead SOIC package for IGBTs and MOSFETs . Also available in 8 Lead PDIP, 14 Lead SOIC, and 14 Lead PDIP.For the new version with our SOI technology we recommend 2ED2109S06F , providing integrated bootstrap diode, better robustness and higher switching frequency

Features

  • Floating channel for bootstrap op.
  • Fully operational to +600 V
  • Tolerant to neg. transient volt.
  • dV/dt immune
  • Gate drive supply: 10 V to 20 V
  • Undervolt. lockout for both channel
  • 3.3, 5, & 15 V logic input compati.
  • Cross-conduction prevention logic
  • Matched prop. delay for both chan.
  • High side out. in phase with IN in.
  • Logic & power ground +/- 5 V offset
  • Internal 540ns dead-time

Documents

Documents

Design resources

Partner solutions

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