NEW
Active and preferred
RoHS Compliant

IQE010N04LM7CGSC

NEW
OptiMOS™ 7 40 V switching optimized power MOSFET in PQFN 3.3x3.3 Source-Down Center Gate Dual-Side Cooled (DSC) package
Data Sheet
package

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IQE010N04LM7CGSC
IQE010N04LM7CGSC
Data Sheet

Product details

  • ID (@25°C) max
    270 A
  • IDpuls max
    1080 A
  • Operating Temperature range
    -55 °C to 175 °C
  • Package
    PQFN 3.3x3.3 Source-Down
  • Polarity
    N
  • QG (typ @4.5V)
    18.9 nC
  • QG (typ @10V)
    39 nC
  • RDS (on) (@4.5V) max
    1.3 mΩ
  • RDS (on) (@10V) max
    1 mΩ
  • Special Features
    Logic Level, Switching optimized, Dual-Side Cooling
  • VDS max
    40 V
  • VGS(th) range
    1.1 V to 1.7 V
  • VGS(th)
    1.4 V
Recommended
OPN
IQE010N04LM7CGSCATMA1
Product Status active and preferred
Infineon Package
PG-WHTFN-9
Package Name N/A
Packing Size 6000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-WHTFN-9
Package Name -
Packing Size 6000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
Infineon latest OptiMOS™ 7 40 V switching-optimized MOSFET offers an unprecedented level of application-optimization, enabling peak performance across a range of applications, including data centers, artificial intelligence, telecommunications, and more. It delivers up to 25% improved conduction loss and up to 20% betterFOM Qg and FOM Qoss vs. OptiMOS™ 6, enabling higher efficiency and power density in soft-switching DC-DC, IBC and 48 V conversion.

Features

  • Application-specific MOSFET optimization
  • Up to 25% lower conduction loss
  • Up to -25% RDS(on) vs. OptiMOS™ 6
  • Controlled charges for switching
  • Up to 20% better FOM Qg, FOM Qoss
  • Source-down dual-side cooled (DSC)
  • PQFN 3.3×3.3 footprint

Benefits

  • Higher power density
  • Higher efficiency at full load
  • High frequency switching enablement
  • Increased thermal performance
  • Lower switching losses in fast designs
  • Simplified paralleling via Center Gate

Documents

Documents

Design resources

Partner solutions

Developer community

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