Active and preferred
RoHS Compliant
Lead-free

S80KS5122GABHB023

Data Sheet
package

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S80KS5122GABHB023
S80KS5122GABHB023
Data Sheet

Product details

  • Density
    512 MBit
  • Family
    KS-2
  • Initial Access Time
    35 ns
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Automotive
  • Technology
    HYPERRAM
Recommended
OPN
S80KS5122GABHB023
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
S80KS5122GABHB023 is a 512 Mb HYPERRAM™ self-refresh DRAM with a 1.8 V HyperBus™ interface, 8-bit DQ and RWDS strobe, using DDR transfers up to 200 MHz (400 MBps) with 35 ns max tACC. It operates from 1.7 V to 2.0 V across -40 to 105°C (AEC-Q100 Grade 2). Linear or wrapped bursts (16 to 128 bytes), partial/full refresh, hybrid sleep and deep power-down are supported in a 24-ball FBGA.

Features

  • HyperBus interface
  • 1.7 V to 2.0 V VCC supply
  • Single or differential clock input
  • 8-bit DDR bus with RWDS strobe
  • 200 MHz maximum clock rate
  • Up to 400 MBps data throughput
  • 35 ns maximum access time tACC
  • Burst: linear or wrapped
  • Wrap bursts: 16/32/64/128 bytes
  • Interface standby ignores I/O pins
  • Active clock stop after tACC+30 ns
  • Hybrid sleep via CR1[5], data kept

Benefits

  • 400 MBps supports fast buffering
  • DDR boosts bandwidth per pin
  • 1.8 V I/O matches low-voltage SoCs
  • RWDS strobe eases timing closure
  • Linear burst fits streaming reads
  • Wrap bursts match cache line fills
  • Standby reduces idle power draw
  • Clock stop saves power on stalls
  • Hybrid sleep keeps RAM contents
  • HS entry in 3 us reduces wake cost
  • HS exit in 100 us improves response
  • Deep power down cuts leakage

Documents

Documents

Design resources

Partner solutions

Developer community

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