Active and preferred
RoHS Compliant
Lead-free

S80KS2563GABHI020

Data Sheet
package
ea.
in stock

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S80KS2563GABHI020
S80KS2563GABHI020
ea.
Data Sheet

Product details

  • Density
    256 MBit
  • Family
    KS-3
  • Initial Access Time
    35 ns
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    xSPI (Octal)
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S80KS2563GABHI020
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
{"en":"S80KS2563GABHI020 is a 256 Mb, 1.8 V HYPERRAM\u2122 self-refresh DRAM with Octal xSPI DDR. It runs to 200 MHz for up to 400 MBps and 35 ns max access time. Linear or wrapped bursts (16128 bytes) are supported, with hybrid sleep and deep power down to 15 b5A at 105b0C. BHI is a 24-ball FBGA tray device rated -40b0C to +85b0C.","zh":"S80KS2563GABHI020为256 Mb、1.8 V的HYPERRAM\u2122自刷新DRAM，采用八线xSPI DDR接口。最高200 MHz，吞吐量达400 MBps，最大访问时间35 ns。

Features

  • Octal xSPI interface, DDR
  • 200 MHz maximum clock rate
  • Up to 400 MBps (3,200 Mbps)
  • 8-bit data bus DQ[7:0]
  • RWDS strobe and write data mask
  • Optional diff clock CK/CK#
  • Hardware reset pin RESET#
  • Linear or wrapped burst 16-128 B
  • Hybrid burst: wrapped then linear
  • Hybrid sleep retains memory data
  • Deep power down stops all refresh
  • 1.7 V to 2.0 V VCC supply

Benefits

  • DDR octal cuts pin count vs 16-bit
  • 400 MBps speeds memory bandwidth
  • 200 MHz supports fast xSPI hosts
  • RWDS improves DDR timing margin
  • Diff clock improves signal integrity
  • RESET# enables robust recovery
  • Burst options optimize bus efficiency
  • Hybrid burst fits cacheline fetches
  • Hybrid sleep lowers power, keeps data
  • Deep power down minimizes standby I
  • Low VCC reduces system power
  • ESD ratings improve handling margin

Documents

Documents

Design resources

Partner solutions

Developer community

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