Active and preferred
RoHS Compliant
Lead-free

S80KS2562GABHB023

Data Sheet
package

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S80KS2562GABHB023
S80KS2562GABHB023
Data Sheet

Product details

  • Density
    256 MBit
  • Family
    KS-2
  • Initial Access Time
    35 ns
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Automotive
  • Technology
    HYPERRAM
Recommended
OPN
S80KS2562GABHB023
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S80KS2562GABHB023 is a 256 Mb HYPERRAM self-refresh DRAM with a 1.8 V HYPERBUS interface and DDR bandwidth up to 400 MBps at 200 MHz (tACC 35 ns). It supports single-ended or differential clocking, configurable linear or wrapped bursts (16 to 128 bytes), and partial or full array refresh. Hybrid sleep and deep power-down reach 15 µA at 105°C. Automotive grade B runs 1.7 V to 2.0 V from -40°C to 105°C.

Features

  • HYPERBUS interface, CS#, RESET#
  • 8-bit DQ[7:0] data bus
  • RWDS strobe + write data mask
  • DDR transfers on both clock edges
  • 200 MHz max clock, 35 ns tACC
  • Up to 400 MBps (3,200 Mbps)
  • Linear and wrapped burst (16-128 B)
  • Drive strength configurable
  • Self-refresh, partial array refresh
  • Interface standby ignores I/O
  • Hybrid sleep retains data, 3 b5s max
  • Deep power down stops refresh

Benefits

  • Easy MCU/FPGA RAM expansion
  • 8-bit bus cuts routing vs x16
  • RWDS simplifies timing + masking
  • DDR boosts bandwidth per pin
  • 200 MHz/35 ns reduces latency
  • 400 MBps supports fast graphics
  • Burst options optimize bus use
  • Drive tuning improves signal SI
  • Partial refresh lowers standby power
  • Standby reduces idle bus toggling
  • Hybrid sleep saves power, keeps data
  • DPD cuts current to b5A level

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }