Active and preferred
RoHS Compliant
Lead-free

S29GL064S90DHVV10

Data Sheet
package
software

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S29GL064S90DHVV10
S29GL064S90DHVV10
Data Sheet

Product details

  • Density
    64 MBit
  • Family
    GL-S
  • Initial Access Time
    90 ns
  • Interface Frequency (SDR/DDR) (MHz)
    NA
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Page Access Time
    15 ns
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
Recommended
OPN
S29GL064S90DHVV10
Product Status active and preferred
Infineon Package
PG-LFBGA-64
Package Name FBGA-64 (002-15537)
Packing Size 520
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-LFBGA-64
Package Name FBGA-64 (002-15537)
Packing Size 520
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S29GL064S90DHVV10 is a 64 Mb (8 MB) parallel NOR flash memory built on Infineon's 65-nm MIRRORBIT™ process. Operating from a single 3.0 V supply with I/O voltages from 1.65 V to VCC, it offers access times as fast as 70 ns. Endurance is 100,000 erase cycles per sector and 20-year data retention. Advanced sector protection, hardware ECC, and secure silicon region enhance reliability. Automotive AEC-Q100 qualification and fortified BGA packaging suit embedded applications.

Features

  • 3.0 V single power supply operation
  • 65-nm MIRRORBIT™ process technology
  • 16-bit or 8/16-bit data bus options
  • 70 ns access time, 15 ns page read time
  • 8-word/16-byte page read buffer
  • 128-word/256-byte write buffer
  • Internal hardware ECC, single bit correction
  • Advanced sector protection
  • 100,000 erase cycles per sector min
  • 20-year data retention typical
  • Automatic sleep and standby modes
  • JEDEC CFI and command set compatible

Benefits

  • 3.0 V simplifies power design
  • 65-nm tech ensures high reliability
  • Flexible bus supports legacy and new designs
  • Fast access boosts system performance
  • Page buffer enables quick data reads
  • Write buffer speeds up programming
  • ECC improves data integrity
  • Multi-level protection enhances security
  • High endurance lowers maintenance cost
  • Long retention secures critical data
  • Low-power modes extend battery life
  • JEDEC compatibility eases integration

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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