Active and preferred
RoHS Compliant
Lead-free

S29GL064S70FHI020

Data Sheet
package
software
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S29GL064S70FHI020
S29GL064S70FHI020
ea.
Data Sheet

Product details

  • Density
    64 MBit
  • Family
    GL-S
  • Initial Access Time
    70 ns
  • Interface Frequency (SDR/DDR) (MHz)
    NA
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Page Access Time
    15 ns
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
Recommended
OPN
S29GL064S70FHI020
Product Status active and preferred
Infineon Package
PG-LFBGA-64
Package Name FBGA-64 (002-15536)
Packing Size 1800
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-LFBGA-64
Package Name FBGA-64 (002-15536)
Packing Size 1800
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S29GL064S70FHI020 is a 64 Mb (8 MB) parallel NOR flash memory built on Infineon's 65-nm MIRRORBIT™ process. It operates from a single 3.0 V supply with I/O voltage from 1.65 V to 3.6 V and delivers 70 ns access time. Robust sector protection and a secure silicon region enable permanent storage. Endurance is rated at 100,000 erase cycles per sector. Industrial temperature support ranges from -40°C to +85°C. JEDEC-compliant, it is ideal for code storage in embedded systems.

Features

  • 3.0 V single power supply operation
  • 65-nm MIRRORBIT™ process technology
  • 16-bit or 8/16-bit data bus options
  • 70 ns access time, 15 ns page read time
  • 8-word/16-byte page read buffer
  • 128-word/256-byte write buffer
  • Internal hardware ECC, single bit correction
  • Advanced sector protection
  • 100,000 erase cycles per sector min
  • 20-year data retention typical
  • Automatic sleep and standby modes
  • JEDEC CFI and command set compatible

Benefits

  • 3.0 V simplifies power design
  • 65-nm tech ensures high reliability
  • Flexible bus supports legacy and new designs
  • Fast access boosts system performance
  • Page buffer enables quick data reads
  • Write buffer speeds up programming
  • ECC improves data integrity
  • Multi-level protection enhances security
  • High endurance lowers maintenance cost
  • Long retention secures critical data
  • Low-power modes extend battery life
  • JEDEC compatibility eases integration

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }