NEW
Active and preferred
RoHS Compliant
Lead-free

S28HL02GTFGBHI053

NEW
Industrial grade 2 Gb 3 V Octal NOR flash
Data Sheet
package

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S28HL02GTFGBHI053
S28HL02GTFGBHI053
Data Sheet

Product details

  • Density
    2048 MBit
  • Family
    HL-T
  • Interface Bandwidth
    266 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / 133
  • Interfaces
    Octal
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Industrial
Recommended
OPN
S28HL02GTFGBHI053XUMA1
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S28HL02GTFGBHI053 is a 2 Gb (2048 Mbit) SEMPER™ NOR flash (HL-T) with JEDEC JESD251 Octal interface for high-speed code and data storage in industrial embedded systems. It operates from 2.7 V to 3.6 V across -40°C to +85°C and supports 133 MHz SDR/DDR reads with up to 266 MByte/s bandwidth. ECC (SECDED), data integrity CRC, and SafeBoot enhance boot reliability and in-field updates.

Features

  • MIRRORBIT™ stores 2 bits per cell
  • Dual-die MCP (DDP) architecture
  • Uniform or hybrid sector architecture
  • 4 KB and 256 KB sector options
  • 256 or 512-byte program buffer
  • 1024-byte OTP secure silicon array
  • JESD251 xSPI compliant interface
  • Octal SDR/DDR with DS data strobe
  • Hamming ECC per 16-byte data unit
  • SECDED: correct 1-bit, detect 2-bit
  • ECC status, trap addr, INT# alert
  • SafeBoot failure signature status

Benefits

  • Higher density in same die size
  • More memory in one MCP footprint
  • Tune sectors for code and data
  • 4 KB erase reduces update time
  • Faster programming improves throughput
  • OTP helps protect keys and IDs
  • JEDEC xSPI eases host integration
  • DS simplifies high-speed reads
  • ECC improves read data reliability
  • 2-bit detect avoids silent faults
  • INT# enables quick error response
  • SafeBoot aids recovery after faults

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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