Active and preferred
RoHS Compliant
Lead-free

S27KL0643DPBHV020

Data Sheet
package

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S27KL0643DPBHV020
S27KL0643DPBHV020
Data Sheet

Product details

  • Density
    64 MBit
  • Family
    KL-3
  • Initial Access Time
    36 ns
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    xSPI (Octal)
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S27KL0643DPBHV020
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
S27KL0643DPBHV020 is a 64 Mb HYPERRAM™ self-refresh DRAM (PSRAM) for high-bandwidth, random-access expansion of embedded systems. It uses an octal xSPI interface with DDR transfers up to 200 MHz (400 MBps) and 35 ns maximum access time, with RWDS for latency indication and read/write strobe. The 3.0 V device runs from 2.7 V to 3.6 V across -40°C to +105°C, and supports deep power down at 15 µA (3.6 V, 105°C) in a 24-ball FBGA.

Features

  • Octal xSPI with CS# and RWDS
  • 8-bit DQ data bus
  • 1.8 V and 3.0 V interface
  • 200 MHz maximum clock rate
  • DDR transfers on both edges
  • Up to 400 MBps data throughput
  • Burst modes: linear and wrapped
  • Wrap bursts: 16/32/64/128 B
  • Hybrid burst: wrap then linear
  • Configurable output drive strength
  • Hybrid Sleep retains memory data
  • Deep power down stops refresh

Benefits

  • Octal xSPI reduces routing effort
  • RWDS strobe simplifies DDR design
  • Dual-voltage I/O fits more MCUs
  • 200 MHz supports fast memory access
  • DDR boosts bandwidth per clock
  • 400 MBps enables high-speed buffers
  • Burst modes tune system efficiency
  • Wrapped bursts reduce bus overhead
  • Hybrid burst aids mixed access
  • Drive strength tuning improves SI
  • Hybrid Sleep saves power, keeps data
  • DPD cuts current in idle states

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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