Active and preferred
RoHS Compliant
Lead-free

S27KL0643DPBHB023

Data Sheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S27KL0643DPBHB023
S27KL0643DPBHB023
Data Sheet

Product details

  • Density
    64 MBit
  • Family
    KL-3
  • Initial Access Time
    36 ns
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    xSPI (Octal)
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Automotive
  • Technology
    HYPERRAM
Recommended
OPN
S27KL0643DPBHB023
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
S27KL0643DPBHB023 is a 64 Mb HYPERRAM™ self-refresh DRAM (PSRAM) using an Octal xSPI DDR interface with RWDS read strobe/write mask and hardware RESET#. It operates from 2.7 V to 3.6 V, supports up to 166 MHz clock rate, and offers linear or wrapped bursts (16 to 128 bytes). AEC-Q100 Grade 2 -40°C to +105°C plus Hybrid Sleep and deep power down to 12 µA reduce memory power in automotive embedded systems.

Features

  • Octal xSPI with CS# and RWDS
  • 8-bit DQ data bus
  • 1.8 V and 3.0 V interface
  • 200 MHz maximum clock rate
  • DDR transfers on both edges
  • Up to 400 MBps data throughput
  • Burst modes: linear and wrapped
  • Wrap bursts: 16/32/64/128 B
  • Hybrid burst: wrap then linear
  • Configurable output drive strength
  • Hybrid Sleep retains memory data
  • Deep power down stops refresh

Benefits

  • Octal xSPI reduces routing effort
  • RWDS strobe simplifies DDR design
  • Dual-voltage I/O fits more MCUs
  • 200 MHz supports fast memory access
  • DDR boosts bandwidth per clock
  • 400 MBps enables high-speed buffers
  • Burst modes tune system efficiency
  • Wrapped bursts reduce bus overhead
  • Hybrid burst aids mixed access
  • Drive strength tuning improves SI
  • Hybrid Sleep saves power, keeps data
  • DPD cuts current in idle states

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }