Active and preferred
RoHS Compliant
Lead-free

S26KL256SDABHV020

Data Sheet
package
software
ea.
in stock

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S26KL256SDABHV020
S26KL256SDABHV020
ea.
Data Sheet

Product details

  • Bus Width
    x8
  • Density
    256 MBit
  • Family
    KL-S
  • Initial Access Time
    96 ns
  • Interface Bandwidth
    200 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 100
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
  • Technology
    HYPERFLASH
Recommended
OPN
S26KL256SDABHV020
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 1690
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 1690
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S26KL256SDABHV020 is a 256 Mb (32 MB) HYPERFLASH™ NOR memory with a high-speed HYPERBUS™ DDR interface and 3.0 V-only operation. It supports up to 100 MHz clock rate for 200 MBps sustained read throughput and 96 ns initial random access. Built on 65 nm MIRRORBIT™ technology, it offers 100,000 program/erase cycles, 20-year retention, advanced sector protection, ECC, CRC, and AEC-Q100 Grade 2 qualification (–40°C to +105°C) for automotive and industrial applications.

Features

  • 3.0 V I/O with 11 bus signals
  • 1.8 V I/O with 12 bus signals
  • Up to 333 MBps sustained read throughput
  • DDR: two data transfers per clock
  • 8-bit data bus (DQ[7:0])
  • 96-ns initial random read access time
  • 512-byte program buffer
  • ECC: 1-bit correction, 2-bit detection
  • Hardware accelerated CRC calculation
  • Secure silicon region (1024-byte OTP)
  • Advanced sector protection methods
  • Low power modes: standby 25 µA, deep

Benefits

  • High throughput enables fast data access
  • DDR boosts system performance
  • 8-bit bus simplifies integration
  • Fast random access reduces latency
  • Large buffer speeds up programming
  • ECC ensures reliable data integrity
  • CRC detects data errors quickly
  • Secure region protects critical data
  • Flexible sector protection enhances security
  • Low power modes extend battery life

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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